PL133-67
Low-Power 2.25V to 3.63V DC to 150MHz 1:6 Fanout Buffer IC
FEATURES
1:6 LVCMOS output fanout buffer for DC to 150MHz
8mA Output Drive Strength
Low power consumption for portable applications
Low input-output delay
Output-Output skew less than 250ps
Low Additive Phase Jitter of 60fs RMS
2.5V to 3.3V, ±10% operation
Operating temperature range from -40°C to 85°C
Available in 16-Pin SOP GREEN/RoHS package
DESCRIPTION
The PL133-67 is an advanced fanout buffer design for
high performance, low-power, small form factor applica-
tions. The PL133-67 accepts a reference clock input from
DC to 150MHz and provides 6 outputs of the same fre-
quency.
The PL133-67 is offered in a TSSOP-16L package and it
offers the best phase noise, additive jitter performance,
and lowest power consumption of any comparable IC.
The PL133-67 outputs can be disabled to a high imped-
ance (tri-state) by pulling low the OE pin. When the OE pin
is high, the outputs are enabled and follow the REF input
signal. When the OE pin is left open, a pull-up resistor on
the chip will default the OE pin to logic 1 so the outputs are
enabled.
BLOCK DIAGRAM AND PACKAGE PINOUT
REF
CLK1
CLK2
CLK3
REF
CLK4
CLK5
CLK6
OE
DNC
CLK0
VDD
GND
CLK1
CLK2
OE^
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
DNC
DNC
CLK5
VDD
GND
CLK4
CLK3
GND
TSSOP-16L
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 •
www.micrel.com
Rev 03/18/11 Page 1
PL133-67
Low-Power 2.25V to 3.63V DC to 150MHz 1:6 Fanout Buffer IC
PIN DESCRIPTIONS
Name
REF
CLK0
CLK1
CLK2
CLK3
CLK4
CLK5
VDD
GND
OE
DNC
TSSOP-16L
1
3
6
7
10
11
14
4, 13
5, 9, 12
8
2, 8, 15, 16
Type
I
O
O
O
O
O
O
P
P
I
-
Description
Input reference frequency.
Buffered clock output
Buffered clock output
Buffered clock output
Buffered clock output
Buffered clock output
Buffered clock output
VDD connection
GND connection
Output Enable Control Input with 130K Pull-Up
Do Not Connect
LAYOUT RECOMMENDATIONS
The following guidelines are to assist you with a performance optimized PCB d esign:
Signal Integrity and Termination
Considerations
- Keep traces short!
- Trace = Inductor. With a capacitive load this equals
ringing!
- Long trace = Transmission Line. Without proper termi-
nation this will cause reflections ( looks like ringing ).
- Design long traces (> 1 inch) as “striplines” or
“microstrips” with defined impedance.
- Match trace at one side to avoid reflections bouncing
back and forth.
Decoupling and Power Supply
Considerations
- Place decoupling capacitors as close as possible
to the VDD pin(s) to limit noise from the power
supply
- Addition of a ferrite bead in series with VDD can
help prevent noise from other board sources
- Value of decoupling capacitor is frequency de-
pendant. Typical values to use are 0.1
F
for de-
signs using frequencies < 50MHz and 0.01F for
designs using frequencies > 50MHz.
( Typical buffer impedance 20 ohm)
Typical CMOS termination
Place Series Resistor as close as possible to CMOS output
CMOS Output Buffer
To CMOS Input
50 ohm line
Connect a 33 ohm series resistor at each of the output clocks to
enhance the stability of the output signal
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax +1(408) 474-1000 •
www.micrel.com
Rev 03/18/11 Page 2
PL133-67
Low-Power 2.25V to 3.63V DC to 150MHz 1:6 Fanout Buffer IC
ABSOLUTE M AXIM UM CONDITIONS
Supply Voltage to Ground Potential ...... –0.5V to 4.6V
DC Input Voltage ............................ V
SS
– 0.5V to 4.6V
Storage Temperature ..........................–65°C to 150°C
Junction Temperature………………………….. 150°C
Static Discharge Voltage
(per MIL-STD-883, Method 3015)…………..> 2000V
OPERATING CONDITIONS
Parameter
V
DD
T
A
Description
Supply Voltage
Commercial Operating Temperature (ambient te mperature)
Industrial Operating Temperature (ambient te mperature)
Load Capacitance, below 100 MHz
C
L
C
IN
REF, CLK[1:6]
t
PU
Load Capacitance between 100 MHz and 134 MHz
Load Capacitance, above 134 MHz
Input Capacitance
Operating Frequency, Input=Output
Power-up time for all V
DD
s to reach minimum specified voltage
(power ramps must be monotonic)
Min.
2.25
0
-40
―
―
―
―
DC
0.05
Max.
3.63
70
85
30
10
5
7
150
50
Unit
V
C
C
pF
pF
pF
pF
MHz
ms
ELECTRICAL CHARACTERISTICS
(Commercial and Industrial Temperature Devices)
Parameter
V
IL
V
IH
I
IL
I
IH
V
OL
V
OH
I
DD
R
PU
Description
Input LOW Voltage
[1]
Input HIGH Voltage
[1]
Input LOW Current
Input HIGH Current
Output LOW Voltage
[2]
Output HIGH Voltage
[2]
Supply Current
OE Pin Pull-Up Resistance
V
IN
= 0V
V
IN
= V
DD
I
OL
= 8 mA
I
OH
= –8 mA
66.67MHz with unloaded outputs
Test Conditions
Min.
–
2.0
–
–
–
2.4
–
100
Max.
0.8
–
50
100
0.4
–
32
–
Unit
V
V
µA
µA
V
V
mA
K
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax +1(408) 474-1000 •
www.micrel.com
Rev 03/18/11 Page 3
PL133-67
Low-Power 2.25V to 3.63V DC to 150MHz 1:6 Fanout Buffer IC
SWITCHING CHARACTERISTICS
(Commercial and Industrial Temperature Devices)
[3 ]
Parameter
t
3
t
4
t
5
t
6
Description
Duty Cycle
[2]
= t2 ÷ t1
Rise Time
[2]
Fall Time
[2]
Output to Output Skew
[2]
Propagation Delay, REF Rising
Edge to CLKX Rising Edge
[2]
Test Conditions
Measured at 1.4V, Input is 50%
Measured between 0.8V and 2.0V
Measured between 0.8V and 2.0V
All outputs equally loaded
Measured at V
DD
/2
Min.
40
–
–
–
1
Typ.
50
–
–
–
5
Max.
60
1.5
1.5
250
9.2
Unit
%
ns
ns
ps
ns
Notes:
1. REF input has a threshold voltage of V
DD
/2
2. Parameter is guaranteed by design and characterization. Not 100% tested in produ ction.
3. All parameters are specified with loaded outputs .
NOISE CHARACTERISTICS
(Commercial and Industrial Temperature Devices)
Parameter
Description
Additive Phase Jitter
Test Conditions
V
DD
=3.3V, Frequency=100MHz
Offset=12KHz ~ 20MHz
Min.
Typ.
60
Max.
Unit
fs
PL133-67 Additive Phase Jitter:
VDD=3.3V, CLK=100MHz, Integration Range 12KHz to 20MHz: 0.059ps typical.
REF Input
-60
-70
-80
-90
Phase Noise (dBc/Hz)
PL133-67 Output
-100
-110
-120
-130
-140
-150
-160
10
100
1000
10000
100000
1000000
10000000
100000000
Offset Frequency (Hz)
When a buffer is used to pass a signal then the buffer will add a little bit of its own noise. The phase noise on the output of the
buffer will be a little bit more than the phase noise in the input signal. To quantify the noise addition in the buffer we compare the
Phase Jitter numbers from the input and the output. The difference is called "Additive Phase Jitter". The formula for the Additive
Phase Jitter is as follows:
Additive Phase Jitter = (Output Phase Jitter) - (Input Phase Jitter)
2
2
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax +1(408) 474-1000 •
www.micrel.com
Rev 03/18/11 Page 4
PL133-67
Low-Power 2.25V to 3.63V DC to 150MHz 1:6 Fanout Buffer IC
SWITCHING WAVEFORMS
Duty Cycle Timing
t
2
t
1
1.4V
1.4V
All Outputs Rise/Fall Time
OUTPUT
t
3
2.0V
0.8V
2.0V
0.8V
t
4
3.3V
V
0V
Output-Output Skew
1.4V
OUTPUT
1.4V
t
5
OUTPUT
Input-Output Propagation Delay
VDD/2
INPUT
OUTPUT
VDD/2
t
6
TEST CIRCUIT
VDD
0.1
F
OUTPUTS
VDD
CLK
C
L OAD
0.1
F
GND
GND
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax +1(408) 474-1000 •
www.micrel.com
Rev 03/18/11 Page 5
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