74HC237
3-to-8 line decoder, demultiplexer with address latches
Rev. 6 — 23 August 2012
Product data sheet
1. General description
The 74HC237 is a high-speed Si-gate CMOS device and is pin compatible with low-power
Schottky TTL (LSTTL). The 74HC237 is specified in compliance with JEDEC
standard no. 7A.
The 74HC237 is a 3-to-8 line decoder, demultiplexer with latches at the three address
inputs (An). The 74HC237 essentially combines the 3-to-8 decoder function with a 3-bit
storage latch. When the latch is enabled (LE = LOW), the 74HC237 acts as a 3-to-8 active
LOW decoder. When the latch enable (LE) goes from LOW-to-HIGH, the last data present
at the inputs before this transition, is stored in the latches. Further address changes are
ignored as long as LE remains HIGH. The output enable input (E1 and E2) controls the
state of the outputs independent of the address inputs or latch operation. All outputs are
HIGH unless E1 is LOW and E2 is HIGH. The 74HC237 is ideally suited for implementing
non-overlapping decoders in 3-state systems and strobed (stored address) applications in
bus-oriented systems.
2. Features and benefits
Combines 3-to-8 decoder with 3-bit latch
Multiple input enable for easy expansion or independent controls
Active HIGH mutually exclusive outputs
Low-power dissipation
ESD protection:
HBM JESD22-A114F exceeds 2 000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from
40 C
to +85
C
and from
40 C
to +125
C
3. Ordering information
Table 1.
Ordering information
Temperature range
74HC237N
74HC237D
74HC237DB
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
Name
DIP16
SO16
SSOP16
Description
plastic dual in-line package; 16 leads (300 mil)
plastic small outline package; 16 leads; body width
3.9 mm
plastic shrink small outline package; 16 leads;
body width 5.3 mm
Version
SOT38-4
SOT109-1
SOT338-1
Type number Package
NXP Semiconductors
74HC237
3-to-8 line decoder, demultiplexer with address latches
4. Functional diagram
4
LE
Y0 15
Y1 14
1 A0
2 A1
3 A2
INPUT
LATCHES
3 TO 8
DECODER
Y2 13
Y3 12
Y4 11
Y5 10
Y6 9
Y7 7
5 E1
6 E2
001aab871
Fig 1.
Functional diagram
DX
4
1
2
4
LE
Y0
Y1
1
2
3
A0
INPUT
A1
LATCHES
A2
Y2
Y3
3 TO 8
DECODER Y4
Y5
Y6
Y7
15
14
13
12
11
10
9
7
4
1
2
E1
5
6
E2
001aab869
C8
0
8D,G
2
0
7
0
1
2
3
4
5
15
14
13
12
11
10
9
7
3
5
6
&
6
7
X/Y
C8
8D,1
8D,2
8D,4
0
1
2
3
4
5
5
6
EN
001aab870
15
14
13
12
11
10
9
7
3
&
6
7
Fig 2. Logic symbol
Fig 3. IEC logic symbol
74HC237
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 6 — 23 August 2012
2 of 17
NXP Semiconductors
74HC237
3-to-8 line decoder, demultiplexer with address latches
A0
A0
LE
LATCH
A0
LE
Y0
Y1
A1
A1
LE
LATCH
A1
LE
Y2
A2
A2
LE
LATCH
A2
LE
Y3
Y4
LE
Y5
Y6
Y7
E1
001aab872
E2
Fig 4.
Logic diagram
5. Pinning information
5.1 Pinning
74HC237
A0
A1
A2
LE
E1
E2
Y7
GND
1
2
3
4
5
6
7
8
001aab868
16 V
CC
74HC237
15 Y0
14 Y1
13 Y2
12 Y3
11 Y4
10 Y5
9
Y6
A0
A1
A2
LE
E1
E2
Y7
GND
1
2
3
4
5
6
7
8
001aan382
16 V
CC
15 Y0
14 Y1
13 Y2
12 Y3
11 Y4
10 Y5
9
Y6
Fig 5.
Pin configuration DIP16 and SO16
Fig 6.
Pin configuration SSOP16
74HC237
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 6 — 23 August 2012
3 of 17
NXP Semiconductors
74HC237
3-to-8 line decoder, demultiplexer with address latches
5.2 Pin description
Table 2.
Symbol
A0 to A2
LE
E1
E2
Y0 to Y7
GND
V
CC
Pin description
Pin
1, 2, 3
4
5
6
8
16
Description
data input
latch enable input (active LOW)
data enable input 1 (active LOW)
data enable input 2 (active HIGH)
ground (0 V)
supply voltage
15, 14, 13, 12, 11, 10, 9, 7 output
6. Functional description
Table 3:
Enable
LE
H
X
X
L
E1
L
H
X
L
E2
H
X
L
H
Function table
Input
A0
X
X
X
L
H
L
H
L
H
L
H
[1]
Output
A1
X
X
X
L
L
H
H
L
L
H
H
A2
X
X
X
L
L
L
L
H
H
H
H
Y0
stable
L
L
H
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
H
Y1
Y2
Y3
Y4
Y5
Y6
Y7
H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
Parameter
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
DIP16 package
SO16 and SSOP16 packages
74HC237
All information provided in this document is subject to legal disclaimers.
Conditions
V
I
<
0.5
V or V
I
> V
CC
+ 0.5 V
V
O
<
0.5
V or V
O
> V
CC
+ 0.5 V
V
O
=
0.5
V to (V
CC
+ 0.5 V)
Min
0.5
-
-
-
-
-
65
[1]
[2]
Max
+7
20
20
25
+50
50
+150
750
500
Unit
V
mA
mA
mA
mA
mA
C
mW
mW
4 of 17
-
-
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 6 — 23 August 2012
NXP Semiconductors
74HC237
3-to-8 line decoder, demultiplexer with address latches
[1]
[2]
For DIP16 package: P
tot
derates linearly with 12 mW/K above 70
C.
For SO16 package: P
tot
derates linearly with 8 mW/K above 70
C.
For SSOP16 package: P
tot
derates linearly with 5.5 mW/K above 60
C.
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol
V
CC
V
I
V
O
T
amb
t/V
Parameter
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
Conditions
Min
2.0
0
0
40
-
-
-
Typ
5.0
-
-
+25
-
1.67
-
Max
6.0
V
CC
V
CC
+125
625
139
83
Unit
V
V
V
C
ns/V
ns/V
ns/V
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
T
amb
= 25
C
Min
V
IH
HIGH-level
input voltage
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
V
IL
LOW-level
input voltage
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
V
OH
HIGH-level
output voltage
V
I
= V
IH
or V
IL
I
O
=
20 A;
V
CC
= 2.0 V
I
O
=
20 A;
V
CC
= 4.5 V
I
O
=
20 A;
V
CC
= 6.0 V
I
O
=
4.0
mA; V
CC
= 4.5 V
I
O
=
5.2
mA; V
CC
= 6.0 V
V
OL
LOW-level
output voltage
V
I
= V
IH
or V
IL
I
O
= 20
A;
V
CC
= 2.0 V
I
O
= 20
A;
V
CC
= 4.5 V
I
O
= 20
A;
V
CC
= 6.0 V
I
O
= 4.0 mA; V
CC
= 4.5 V
I
O
= 5.2 mA; V
CC
= 6.0 V
-
-
-
-
-
0
0
0
0.15
0.16
0.1
0.1
0.1
0.26
0.26
-
-
-
-
-
0.1
0.1
0.1
0.33
0.33
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
V
V
V
V
V
1.9
4.4
5.9
3.98
5.48
2.0
4.5
6.0
4.32
5.81
-
-
-
-
-
1.9
4.4
5.9
3.84
5.34
-
-
-
-
-
1.9
4.4
5.9
3.7
5.2
-
-
-
-
-
V
V
V
V
V
1.5
3.15
4.2
-
-
-
Typ
1.2
2.4
3.2
0.8
2.1
2.8
Max
-
-
-
0.5
1.35
1.8
T
amb
=
40 C
to
+85
C
Min
1.5
3.15
4.2
-
-
-
Max
-
-
-
0.5
1.35
1.8
T
amb
=
40 C
to Unit
+125
C
Min
1.5
3.15
4.2
-
-
-
Max
-
-
-
0.5
1.35
1.8
V
V
V
V
V
V
74HC237
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 6 — 23 August 2012
5 of 17
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