MIC4223/MIC4224/MIC4225
Dual 4A, 4.5V to 18V, 15ns Switch Time,
Low-Side MOSFET Drivers with Enable
General Description
The MIC4223/MIC4224/MIC4225 are a family of a dual 4A,
High-Speed, Low-side MOSFET drivers with logic-level
driver enables. The devices are fabricated on Micrel’s
Bipolar/CMOS/DMOS (BCD) process and operate from a
4.5V to 18V supply voltage. The devices parallel Bipolar
and CMOS output stage architecture provides high-current
throughout the MOSFETs Miller Region allowing the driver
to sink and source 4A of peak current from a 12V supply
and quickly charge and discharge a 2000pF load
capacitance in under 15ns, while allowing the outputs to
swing within 0.3V of V
DD
and 0.16V of ground.
The MIC4223/MIC4224/MIC4225 driver and enable inputs
feature TTL and CMOS logic-level thresholds which are
independent of supply voltage. Each driver features a
dedicated active-high enable input which is internally
pulled high to V
DD
through 100kΩ, allowing the pins to be
left unconnected if it is not required to disable the driver
outputs. The driver inputs have been designed to protect
against ground bounce and are protected to withstand -5V
of voltage swing at -40mA. Driver outputs are also
protected to withstand 500mA of reverse current.
The MIC4223/MIC4224/MIC4225 are available in three
configurations using industry standard pin out; dual
inverting (MIC4223), dual non-inverting (MIC4224) and
complimentary (MIC4225). They are available in 8-pin
SOIC and thermally enhanced e-PAD 8-pin MSOP and
support operating junction temperatures from -40°C to
+125°C.
Features
•
4.5V to 18V supply voltage operating range
•
High peak source/sink current
– ±3A at V
DD
= 8V
– ±4A at V
DD
= 12V
•
15ns/15ns Rise and Fall times with 2000pF load
•
25ns/35ns (Rising/Falling) input propagation delay
•
20ns/45ns (Rising/Falling) enable propagation delay
•
Active-high driver enable inputs with 100kΩ pull-ups
•
CMOS and TTL logic input and enable thresholds
independent of supply voltage
•
Driver input protection to -5V at -40mA
•
Output Latch-up protection to >500mA reverse current
•
Industry standard pin out with two package options
– ePAD MSOP-8 (θ
JA
= 60°C/W)
– 8-pin SOIC (θ
JA
= 120°C/W)
•
Available in dual-inverting (MIC4223), dual non-
inverting (MIC4224) and complementary (MIC4225)
•
Dual output drive by paralleling channels
•
-40°C to +125°C operating junction temperature range
Block Diagram
Applications
•
•
•
•
•
•
•
•
High-Efficiency MOSFET switching
Switch mode power supplies
DC-to-DC converters
Motor and solenoid drivers
Clock and line drivers
Synchronous rectifiers
Pulse transformer drive
Class D switching amplifiers
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
June 2009
M9999-061109-A
(408) 944-0800
Micrel, Inc.
MIC4223/MIC4224/MIC4225
Ordering Information
Part Number
MIC4223YM
MIC4223YMME
MIC4224YM
MIC4224YMME
MIC4225YM
MIC4225YMME
Configuration
Dual Inverting
Dual Inverting
Dual Non-inverting
Dual Non-inverting
Inverting + Non-inverting
Inverting + Non-inverting
Junction Temp. Range
–40° to +125°C
–40° to +125°C
–40° to +125°C
–40° to +125°C
–40° to +125°C
–40° to +125°C
Package
8-pin SOIC
8-pin EPAD-MSOP
8-pin SOIC
8-pin EPAD-MSOP
8-pin SOIC
8-pin EPAD-MSOP
Lead Finish
Pb-Free
Pb-Free
Pb-Free
Pb-Free
Pb-Free
Pb-Free
Pin Configuration
8-Pin SOIC (YM)
8-Pin ePAD MSOP (YMME)
8-Pin SOIC (YM)
8-Pin ePAD MSOP (YMME)
8-Pin SOIC (YM)
8-Pin ePAD-MSOP (YMME)
Pin Description
Pin Number
1
Pin Name
ENA
Pin Function
Enable pin for output A. TTL/CMOS-compatible logic input. A logic-level high enables the
device. An internal pull-up enables the part if pin is open. A logic-level low disables the device
and the output will be low regardless of the input state.
Control Input A: TTL/CMOS-compatible logic input. Connect to V
DD
or ground if not used and
connect ENA to ground to disable driver A.
Ground
Control Input B: TTL/CMOS compatible logic input. Connect to V
DD
or ground if not used and
connect ENB to ground to disable driver B.
Output B: Parallel Bipolar/CMOS output.
Voltage Supply Input: +4.5V to +18V
Output A: Parallel Bipolar/CMOS output.
Enable pin for output B. TTL/CMOS-compatible logic input. A logic-level high enables the
device. An internal pull-up enables the part if pin is open. A logic-level low disables the device
and the output will be low regardless of the input state.
Exposed thermal pad for ePad MSOP package only (Not available on SOIC-8L package).
Connect to ground. Must make a full connection to the ground plane to maximize thermal
performance of the package.
2
3
4
5
6
7
8
INA
GND
INB
OUTB
VDD
OUTA
ENB
EP
GND
June 2009
2
M9999-061109-A
(408) 944-0800
Micrel, Inc.
MIC4223/MIC4224/MIC4225
Absolute Maximum Ratings
(1)
Supply Voltage (V
DD
)....................................................+20V
Input Voltage (V
INA
, V
INB
) ................ V
DD
+ 0.3V to GND - 5V
Enable Voltage (V
ENA
, V
ENB
)…..…….... ...0.3V to V
DD
+ 0.3V
Junction Temperature (T
J
) .........................-55°C to +150°C
Storage Temperature ................................–65°C to +150°C
Lead Temperature (10 sec.)....................................... 300°C
ESD Rating................................. HBM = 2kV, MM = 200V
(3)
Operating Ratings
(2)
Supply Voltage (V
DD
)..................................... +4.5V to +18V
Junction Temperature (T
J
) ........................ –40°C to +125°C
Package Thermal Resistance
EPAD MSOP (θ
JA
) .............................................60°C/W
SOIC (θ
JA
) ........................................................120°C/W
Electrical Characteristics
4.5V
≤
V
DD
≤
18V; C
L
= 2000pF. T
A
= 25°C, bold values indicate full operating junction temperature range, unless noted.
Symbol
Input
V
IH
V
IL
Hysteresis
I
IN
Input Current
0
≤
V
IN
≤
V
DD
V
IN
= -5V
Output
V
OH
V
OL
RO
IPK
I
t
R
t
F
t
D1
t
D2
V
EN_H
V
EN_L
Hysteresis
R
EN
t
D3
t
D4
I
SH
I
SL
Enable Impedance
Propagation Delay Time
Propagation Delay Time
Power Supply Current
Power Supply Current
V
DD
= 18V, V
ENA
= V
ENB
= GND
C
L
= 2000pF
C
L
= 2000pF
V
INA
= V
INB
= 3.0V, V
ENA
= V
ENB
= open
V
INA
= V
INB
= 0.0V, V
ENA
= V
ENB
= open
High Output Voltage
Low Output Voltage
Output Resistance – Source
Output Resistance – Sink
Peak Output Current
Latch-Up Protection
Rise Time
Fall Time
Delay Time
Delay Time
High Level Enable Voltage
Low Level Enable Voltage
I
OUT
= -10mA, V
DD
= 18V
I
OUT
= 10mA, V
DD
= 18V
I
OUT
= -10mA, V
DD
= 18V
I
OUT
= 10mA, V
DD
= 18V
V
DD
= 8V
V
DD
= 12V
Withstand reverse current
Test Figure 1; C
L
= 2000pF
Test Figure 1; C
L
= 2000pF
Test Figure 1; C
L
= 2000pF
Test Figure 1; C
L
= 2000pF
LO to HI transition
HI to LO transition
2.4
Switching Time
15
15
25
35
1.9
1.55
0.35
100
20
45
1.7
0.7
60
150
2.5
1.5
0.8
40
40
45
50
ns
ns
ns
ns
V
V
V
kΩ
ns
ns
mA
mA
30
16
±3
±4
>500
mA
V
DD
- 0.45
0.30
45
30
V
V
Ω
A
–1
–10
-40
Logic 1 Input Voltage
Logic 0 Input Voltage
2.4
2.2
1.95
0.25
1
10
0.8
V
V
V
µA
µA
mA
Parameter
Condition
Min
Typ
Max
Units
Enable (ENA, ENB)
Power Supply
Notes:
1. Exceeding the absolute maximum rating may damage the device.
2. The device is not guaranteed to function outside its operating rating.
3. Devices are ESD sensitive. Handling precautions recommended. Human body model, 1.5kΩ in series with 100pF.
June 2009
3
M9999-061109-A
(408) 944-0800
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
