74HC377; 74HCT377
Octal D-type flip-flop with data enable; positive-edge trigger
Rev. 3 — 25 September 2013
Product data sheet
1. General description
The 74HC377; 74HCT377 is an octal positive-edge triggered D-type flip-flop. The device
features clock (CP) and data enable (E) inputs. When E is LOW, the outputs Qn assume
the state of their corresponding Dn inputs that meet the set-up and hold time requirements
on the LOW-to-HIGH clock (CP) transition. Input E must be stable one set-up time prior to
the LOW-to-HIGH transition for predictable operation. Inputs include clamp diodes that
enable the use of current limiting resistors to interface inputs to voltages in excess of V
CC
.
2. Features and benefits
Common clock and master reset
Eight positive edge-triggered D-type flip-flops
Complies with JEDEC standard no. 7A
Input levels:
For 74HC377: CMOS level
For 74HCT377: TTL level
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V.
Multiple package options
Specified from
40 C
to +85
C
and from
40 C
to +125
C
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74HC377N
74HCT377N
74HC377D
74HCT377D
74HC377DB
74HCT377DB
74HC377PW
74HCT377PW
40 C
to +85
C
40 C
to +85
C
SSOP20
plastic shrink small outline package; 20 leads; body width
5.3 mm
SOT339-1
SOT360-1
40 C
to +85
C
SO20
plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
40 C
to +85
C
DIP20
Description
plastic dual in-line package; 20 leads (300 mil)
Version
SOT146-1
Type number
TSSOP20 plastic thin shrink small outline package; 20 leads; body
width 4.4 mm
NXP Semiconductors
74HC377; 74HCT377
Octal D-type flip-flop with data enable; positive-edge trigger
4. Functional diagram
3
4
7
8
D0
Q0
Q1
Q2
FF1
to
FF8
2
5
6
9
D1
D2
D3
OUTPUTS
Q3
13
D4
14
D5
17
D6
18
D7
Q4
12
Q5
15
Q6
16
Q7
19
1
E
11 CP
mna606
Fig 1.
Functional diagram
11
1
11
3
4
7
8
13
14
17
18
CP
D0
D1
D2
D3
D4
D5
D6
D7
E
1
mna918
1C2
G1
3
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
2
5
6
9
12
15
16
19
17
18
4
7
8
13
14
2D
2
5
6
9
12
15
16
19
mna919
Fig 2.
Logic symbol
Fig 3.
IEC logic symbol
74HC_HCT377
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 25 September 2013
2 of 19
NXP Semiconductors
74HC377; 74HCT377
Octal D-type flip-flop with data enable; positive-edge trigger
D0
D1
D2
D3
D4
D5
D6
D7
E
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
FF1
CP
FF2
FF3
FF4
FF5
FF6
FF7
FF8
Q0
Q1
Q2
Q3
Q4
Q5
Q6
mna610
Q7
Fig 4.
Logic diagram
74HC_HCT377
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 25 September 2013
3 of 19
NXP Semiconductors
74HC377; 74HCT377
Octal D-type flip-flop with data enable; positive-edge trigger
5. Pinning information
5.1 Pinning
E
Q0
D0
D1
Q1
Q2
D2
D3
Q3
1
2
3
4
5
6
7
8
9
20 V
CC
19 Q7
18 D7
17 D6
377
16 Q6
15 Q5
14 D5
13 D4
12 Q4
11 CP
mna917
GND 10
Fig 5.
Pin configuration
5.2 Pin description
Table 2.
Symbol
E
Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7
D0, D1, D2, D3, D4, D5, D6, D7
GND
CP
V
CC
Pin description
Pin
1
2, 5, 6, 9, 12, 15, 16, 19
3, 4, 7, 8, 13, 14, 17, 18
10
11
20
Description
data enable input (active LOW)
flip-flop output
data input
ground (0 V)
clock input (LOW-to-HIGH, edge triggered)
supply voltage
6. Functional description
Table 3.
Function table
[1]
Inputs
CP
load “1”
load “0”
hold (do nothing)
X
[1]
H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;
X = don’t care;
= LOW-to-HIGH clock transition.
Operating modes
Outputs
E
l
l
h
H
Dn
h
l
X
X
Qn
H
L
no change
no change
74HC_HCT377
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 25 September 2013
4 of 19
NXP Semiconductors
74HC377; 74HCT377
Octal D-type flip-flop with data enable; positive-edge trigger
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V)
Symbol
V
CC
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
Parameter
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
T
amb
=
40 C
to +125
C
DIP20 package
SO20, SSOP20, TSSOP20
[1]
[2]
[3]
[2]
[3]
Conditions
V
I
<
0.5
V or V
I
> V
CC
+ 0.5 V
V
O
<
0.5
V or V
O
> V
CC
+ 0.5 V
0.5
V < V
O
< V
CC
+ 0.5 V
[1]
[1]
Min
0.5
-
-
-
-
50
65
-
-
Max
+7
20
20
25
50
-
+150
750
500
Unit
V
mA
mA
mA
mA
mA
C
mW
mW
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For DIP20 package: above 70
C
the value of P
tot
derates linearly with 12 mW/K.
For SO20 package: above 70
C
the value of P
tot
derates linearly with 8 mW/K.
For SSOP20 and TSSOP20 packages: above 60
C
the value of P
tot
derates linearly with 5.5 mW/K.
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter
V
CC
V
I
V
O
T
amb
t/V
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
Conditions
Min
2.0
0
0
40
-
-
-
74HC377
Typ
5.0
-
-
-
-
1.67
-
Max
6.0
V
CC
V
CC
+125
625
139
83
Min
4.5
0
0
40
-
-
-
74HCT377
Typ
5.0
-
-
-
-
1.67
-
Max
5.5
V
CC
V
CC
+125
-
139
-
V
V
V
C
ns/V
ns/V
ns/V
Unit
74HC_HCT377
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 25 September 2013
5 of 19
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