CAUTION: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional
operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
NOTE:
3.
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Analog Specifications
SYMBOL
R
TOTAL
Over recommended operating conditions unless otherwise stated.
TEST CONDITIONS
W option
U option
MIN
TYP
(Note 1)
10
50
-20
V-
V- = -5.5V; V
CC
= +5.5V
Wiper current = (V
CC
- V-)/R
TOTAL
70
10/10/25
Voltage at pins; V- to V
CC
-1
0.1
1
+20
V
CC
200
MAX
UNIT
k
k
%
V
pF
µA
PARAMETER
R
H
to R
L
Resistance
R
H
to R
L
Resistance Tolerance
V
RH,
V
RL
R
W
C
H
/C
L
/C
W
I
LkgDCP
R
H
, R
L
Terminal Voltage
Wiper Resistance
Potentiometer Capacitance (Note 13)
Leakage on R
H
, R
L
, R
W
pins
VOLTAGE DIVIDER MODE
(V- @ R
L
; V
CC
@ R
H
; Voltage at R
W
= V
RW
unloaded)
INL
(Note 6)
DNL
(Note 5)
ZSerror
(Note 3)
FSerror
(Note 4)
TC
V
(Notes 7, 13)
Integral Non-linearity
Differential Non-linearity
Zero-scale Error
W, U options
W option
U option
Full-scale Error
W option
U option
Ratiometric Temperature Coefficient
DCP register set from 16 to 120d, T = -40°C to
+85°C
-1
-0.5
0
0
-4
-2
1
0.5
-1
-0.5
±4
1
0.5
4
2
0
0
LSB
(Note 2)
LSB
(Note 2)
LSB
(Note 2)
LSB
(Note 2)
ppm/°C
RESISTOR MODE
(Measurements between R
W
and R
L
with R
H
not connected, or between R
W
and R
H
with R
L
not connected)
RINL
(Note 11)
RDNL
(Note 10)
Roffset
(Note 9)
Integral Non-linearity
Differential Non-linearity
Offset
DCP register set to 00 hex, W option
DCP register set to 00 hex, U option
TC
R
Resistance Temperature Coefficient
(Notes 12, 13)
DCP register set from 16 to 127d, T = -40°C to
+85°C
DCP register set between 20 hex and 7F hex.
Monotonic over all tap positions
-1
-0.5
0
0
2
0.5
±50
1
0.5
5
2
MI
(Note 8)
MI
(Note 8)
MI
(Note 8)
MI
(Note 8)
ppm/°C
FN6127 Rev 0.00
August 16, 2005
Page 3 of 10
ISL23711
Operating Specifications
Over the recommended operating conditions unless otherwise specified.
SYMBOL
I
CC1
I
V-
I
SB
PARAMETER
V
CC
Supply Current, Volatile
Write/Read
TEST CONDITIONS
f
SCL
= 400kHz; SDA = Open; (for I
2
C, Active,
Read and Write states only)
-100
MIN
TYP
(Note 1)
MAX
200
-1
500
300
-500
-300
-10
1
2.5
-1
10
UNIT
A
A
nA
nA
nA
nA
µA
µs
V
V- Supply Current, Volatile Write/Read f
SCL
= 400kHz; SDA = Open; (for I
2
C, Active,
Read and Write states only)
V
CC
Current (Standby)
V
CC
= +5.5V, I
2
C Interface in Standby State
V
CC
= +3.6V, I
2
C Interface in Standby State
V- = -5.5V, I
2
C Interface in Standby State
V- = -2.7V, I
2
C Interface in Standby State
I
V-SB
V- Current (Standby)
I
LkgDig
t
DCP
(Note 13)
Vpor
Leakage Current, at Pins SDA, SCL,
A0, and A1
DCP Wiper Response Time
Power-on Recall for V
CC
Voltage at pin from GND to V
CC
SCL falling edge of last bit of DCP Data Byte to
wiper change
SERIAL INTERFACE SPECS
V
IL
V
IH
Hysteresis
V
OL
Cpin
(Note 14)
f
SCL
t
IN
t
AA
t
BUF
A0, A1, SDA, and SCL Input Buffer
LOW Voltage
A0, A1, SDA, and SCL Input Buffer
HIGH Voltage
SDA and SCL Input Buffer Hysteresis
SDA Output Buffer LOW Voltage,
Sinking 4mA
A0, A1, SDA, and SCL Pin
Capacitance
SCL Frequency
Pulse Width Suppression Time at SDA Any pulse narrower than the max spec is
and SCL Inputs
suppressed
SCL Falling Edge to SDA Output Data
Valid
Time the Bus Must be Free Before the
Start of a New Transmission
Clock LOW Time
Clock HIGH Time
START Condition Setup Time
START Condition Hold Time
Input Data Setup Time
Input Data Hold Time
STOP Condition Setup Time
STOP Condition Setup Time
SCL falling edge crossing 30% of V
CC
, until SDA
exits the 30% to 70% of V
CC
window
SDA crossing 70% of V
CC
during a STOP
condition, to SDA crossing 70% of V
CC
during
the following START condition
Measured at the 30% of V
CC
crossing
Measured at the 70% of V
CC
crossing
SCL rising edge to SDA falling edge. Both
crossing 70% of V
CC
From SDA falling edge crossing 30% of V
CC
to
SCL falling edge crossing 70% of V
CC
From SDA exiting the 30% to 70% of V
CC
window, to SCL rising edge crossing 30% of V
CC
From SCL rising edge crossing 70% of V
CC
to
SDA entering the 30% to 70% of V
CC
window
From SCL rising edge crossing 70% of V
CC
, to
SDA rising edge crossing 30% of V
CC
From SDA rising edge to SCL falling edge. Both
crossing 70% of V
CC
1300
-0.3
0.7*V
CC
0.05*
V
CC
0
0.4
10
400
50
900
0.3*V
CC
V
CC
+
0.3
V
V
V
V
pF
kHz
ns
ns
ns
t
LOW
t
HIGH
t
SU:STA
t
HD:STA
t
SU:DAT
t
HD:DAT
t
SU:STO
t
HD:STO
1300
600
600
600
100
0
600
600
ns
ns
ns
ns
ns
ns
ns
ns
FN6127 Rev 0.00
August 16, 2005
Page 4 of 10
ISL23711
Operating Specifications
Over the recommended operating conditions unless otherwise specified.
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