DATASHEET
Frequency Generator and Integrated Buffers
for Celeron & PII/III
TM
Recommended Application:
810/810E and 815 type chipset.
Pin Configuration
*FS2//REF0
VDD
X1
X2
GND
GND
3V66-0
3V66-1
3V66-2
VDD
VDD
PCICLK_F
PCICLK0
GND
PCICLK1
PCICLK2
GND
PCICLK3
PCICLK4
PCICLK5
VDD
VDD
GND
GND
48MHz_0
48MHz_1
VDD
FS0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
ICS9250-27
Output Features:
•
•
•
•
•
•
•
3 CPU (2.5V) (up to 133MHz achievable through I
2
C)
9 SDRAM (3.3V) (up to 133MHz achievable
through I
2
C)
7 PCI (3.3 V) @33.3MHz
2 IOAPIC (2.5V) @ 33.3 MHz
3 Hublink clocks (3.3 V) @ 66.6 MHz
2 (3.3V) @ 48 MHz (Non spread spectrum)
1 REF (3.3V) @ 14.318 MHz
Features:
•
•
•
•
•
Supports spread spectrum modulation,
0 to -0.5% down spread.
I
2
C support for power management
Efficient power management scheme through PD#
Uses external 14.138 MHz crystal
Alternate frequency selections available through I
2
C
control.
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
GND
IOAPIC0
IOAPIC1
VDDL
CPUCLK0
VDDL0
CPUCLK1
CPUCLK2
GNDL
GND
SDRAM0
SDRAM1
VDD
SDRAM2
SDRAM3
GND
SDRAM4
SDRAM5
VDD
SDRAM6
SDRAM7
GND
SDRAM_F
VDD
PD#
SCLK
SDATA
FS1
56-Pin 300mil SSOP
* This input has a 50KΩ pull-down to GND.
Block Diagram
Functionality
X1
X2
XTAL
OSC
PLL1
Spread
Spectrum
REF0
FS2
X
X
FS 1
0
0
1
1
1
1
FS0
0
1
0
1
0
1
ICS9250-27
Function
Tristate
Test
Active CPU = 66MHz
SDRAM = 100MHz
Active CPU = 100MHz
SDRAM = 100MHz
Active CPU = 133MHz
SDRAM = 133MHz
Active CPU = 133MHz
SDRAM = 100MHz
/2
/3
3
VDDL
CPU66/100/133 (2:0)
3V66 (2:0)
SDRAM (7:0)
SDRAM_F
0
0
1
1
FS (2:0)
PD#
Control
Logic
3
8
SDATA
SCLK
Config
Reg
/2
6
PCICLK (5:0)
PCICLK_F
/2
PLL2
2
IOAPIC (1:0)
VDDL
Power Groups
AVDD = Pin 22 Analog power for PLL
AGND = Pin 23 Analog ground
VDD48 = Pin 27 Analog power for 48MHz PLL
GND = Pin 24 Analog ground for 48MHz PLL
48MHz (1:0)
2
IDT
TM
Frequency Generator and Integrated Buffers for Celeron & PII/III
TM
0395F—01/25/10
1
ICS9250-27
Frequency Generator and Integrated Buffers for Celeron & PII/III
TM
General Description
The
ICS9250-27
is a single chip clock solution for 810/810E and 815 type chipset. It provides all necessary clock
signals for such a system.
Spread spectrum may be enabled through I
2
C programming. Spread spectrum typically reduces EMI by 8dB to 10
dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9250-
27 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and
temperature variations.
Pin Description
PIN NUMBER
1
3
4
PIN NAME
FS2
REF0
X1
X2
TYPE
IN
OUT
IN
OUT
PWR
OUT
PWR
OUT
OUT
OUT
OUT
IN
I/O
IN
IN
OUT
OUT
OUT
PWR
OUT
DESCRIPTION
Function Select pin. Determines CPU frequency, all output functionality
3.3V, 14.318MHz reference clock output.
Cr ystal input, has inter nal load cap (33pF) and feedback
resistor from X2
Cr ystal output, nominally 14.318MHz. Has inter nal load
cap (33pF)
Ground pins for 3.3V supply
3.3V Fixed 66MHz clock outputs for HUB
3 . 3 V p ow e r s u p p l y
Free r unning 3.3V PCI clock output
3.3V PCI clock outputs
3.3V Fixed 48MHz clock outputs for USB
3.3V fixed 48MHz clock output. Stronger output for graphics/video
interface (minimum 1V/ns edge rate)
Function Select pins. Determines CPU frequency, all output
functionality. Please refer to Functionality table on page 1
Data pin for I
2
C circuitr y 5V tolerant
Clock pin of I
2
C circuitr y 5V tolerant
Asynchronous active low input pin used to power down the device
into a low power state. The inter nal clocks are disabled and the VCO
a n d t h e c r y s t a l a r e s t o p p e d . T h e l a t e n c y o f t h e p ow e r d ow n w i l l n o t
b e g r e a t e r t h a n 3 m s.
3.3V output r unning 100MHz. All SDRAM outputs can be tur ned off
t h r o u g h I
2
C
3 . 3 V f r e e r u n n i n g 1 0 0 M H z S D R A M , c a n n o t b e t u r n e d o f f t h r o u g h I
2
C
2.5V Host bus clock output. 66MHz, 100MHz or 133MHz depending
o n F S p i n s.
2.5V power suypply for CPU & IOAPIC
2 . 5 V c l o ck o u t p u t s r u n n i n g a t 3 3 . 3 M H z .
5, 6, 14, 17, 23,
24, 35, 41, 47, GND
48, 56
9, 8, 7
2, 10, 11, 21,
22, 27, 33, 38,
44
12
20, 19, 18, 16,
15, 13
25
26
29, 28
30
31
32
36, 37, 39, 40,
42, 43, 45, 46
34
49, 50, 52
51, 53
54, 55
3V66 (2:0)
VDD
PCICLK_F
PCICLK (5:0)
48MHz_0
48MHz_1
FS (1:0)
SDATA
SCLK
PD#
SDRAM (7:0)
SDRAM_F
CPUCLK
(2:0)
VDDL
IOAPIC (1:0)
IDT
TM
Frequency Generator and Integrated Buffers for Celeron & PII/III
TM
0395F—01/25/10
2
ICS9250-27
Frequency Generator and Integrated Buffers for Celeron & PII/III
TM
Power Down Waveform
Note
1.
After PD# is sampled active (Low) for 2 consective rising edges of CPUCLKs, all
the output clocks are driven Low on their next High to Low tranistiion.
2.
Power-up latency <3ms.
3.
Waveform shown for 100MHz
Maximum Allowed Current
815
Condition
Powerdown Mode
(PWRDWN# = 0
Full Active 66MHz
FS[2:0] = 010
Full Active 100MHz
FS[2:0] = 011
Full Active 133MHz
FS[2:0] = 111
Max 2.5V supply consumption
Max discrete cap loads,
Vddq2 = 2.625V
All static inputs = Vddq3 or GND
10mA
70mA
100mA
Max 2.5V supply consumption
Max discrete cap loads,
Vddq2 = 3.465V
All static inputs = Vddq3 or GND
10mA
280mA
280mA
Clock Enable Configuration
PD#
0
1
CPUCLK
LOW
ON
SDRAM
LOW
ON
IOAPIC
LOW
ON
66MHz
LOW
ON
PCICLK
LOW
ON
REF,
48MHz
LOW
ON
Osc
OF F
ON
VCOs
OFF
ON
IDT
TM
Frequency Generator and Integrated Buffers for Celeron & PII/III
TM
0395F—01/25/10
3
ICS9250-27
Frequency Generator and Integrated Buffers for Celeron & PII/III
TM
Truth Table
FS2
X
X
0
0
1
1
FS1 FS0
0
0
1
1
1
1
0
1
0
1
0
1
CPU
Tristate
TCLK/2
66.6 MHz
100 MHz
133 MHz
133 MHz
SDRAM
Tristate
TCLK/2
100 MHz
100 MHz
133 MHz
100 MHz
3V66
Tristate
TCLK/3
66.6
MHz
66.6
MHz
66.6
MHz
66.6
MHz
PCI
Tristate
TCLK/6
33.3 MHz
33.3 MHz
33.3 MHz
33.3 MHz
48MHz
Tristate
TCLK/2
48 MHz
48 MHz
48 MHz
48 MHz
REF
Tristate
TCLK
14.318
MHz
14.318
MHz
14.318
MHz
14.318
MHz
IOAPIC
Tristate
TCLK/6
33.3
MHz
33.3
MHz
33.3
MHz
33.3
MHz
Byte 0: Control Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin#
26
25
49
Name
Reserved ID
Reserved ID
Reserved ID
Reserved ID
SpreadSpectrum
(1=On/0=Off)
48MHz 1
48MHz 0
CPUCLK2
PWD
0
0
0
0
1
1
1
1
Description
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
Note: Reserved ID bits must be wirtten as "0".
Byte 1: Control Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin#
36
37
39
40
42
43
45
46
Name
SDRAM7
SDRAM6
SDRAM5
SDRAM4
SDRAM3
SDRAM2
SDRAM1
SDRAM0
PWD
1
1
1
1
1
1
1
1
Description
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
Notes:
1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be
configured at power-on and are not expected to be configured during the normal modes of operation.
2. PWD = Power on Default
IDT
TM
Frequency Generator and Integrated Buffers for Celeron & PII/III
TM
0395F—01/25/10
4
ICS9250-27
Frequency Generator and Integrated Buffers for Celeron & PII/III
TM
Byte 2: Control Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
B it 4
Bit 3
B it 2
Bit 1
Bit 0
Pin#
9
20
19
18
16
15
13
-
Name
3V66-2 (AGP)
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0
Undefined bit
PWD
1
1
1
1
1
1
1
X
Description
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
Notes:
1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be
configured at power-on and are not expected to be configured during the normal modes of operation.
2. PWD = Power on Default
3. Undefined bit can be wirtten with either a "1" or "0".
Byte 3: ICS Reserved Functionality and frequency select register (Default as noted in PWD)
Bit
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
ICS Reserved bit (Note 2)
ICS Reserved bit (Note 2)
ICS Reserved bit (Note 2)
ICS Reserved bit (Note 2)
ICS Reserved bit (Note 2)
Undefined bit (Note 3)
Undefined bit (Note 3)
Bit 0
0
0
0
Bit 0
0
1
1
1
1
FS0
0
1
0
1
0
1
0
1
FS1
0
0
1
1
0
0
1
1
Desctiption
PWD
0
0
0
0
0
X
X
CPUCLK SDRAM
MHz
MHz
66.66
100.0
133.32
133.32
66.66
100.0
133.32
133.32
100.0
100.0
133.32
100.0
100.0
100.0
133.32
133.32
3V66
MHz
66.66
66.66
66.66
66.66
66.66
66.66
66.66
66.66
PCICLK IOAPIC
MHz
MHz
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
0
Note 1
Note 1:
For system operation, the BSEL lines of the CPU will program FS0, FS2 for the appropriate CPU speed, always
with SDRAM = 100MHz. After BIOS verifies the SDRAM is PC133 speed, then bit 0 can be written from the
default 0 to 1 to change the SDRAM output frequency from 100MHz to 133MHz. This will only change if the CPU
is at the 133MHz FSB speed as shown in this table. The CPU, 3v66, PCI, and IOAPIC clocks will be glitch free
during this transition, and only SDRAM will change.
Note 2: "ICS RESERVED BITS" must be writtern as "O".
Note3:
Undefined bits can be written either as "1 or 0"
IDT
TM
Frequency Generator and Integrated Buffers for Celeron & PII/III
TM
0395F—01/25/10
5
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