DATASHEET
CLOCK MULTIPLIER AND JITTER ATTENUATOR
Description
The ICS2059-02 is a VCXO (Voltage Controlled Crystal
Oscillator) based clock multiplier and jitter attenuator
designed for system clock distribution applications.
This monolithic IC, combined with an external
inexpensive quartz crystal, can be used to replace a
more costly hybrid VCXO retiming module. A dual input
mux is also provided.
By controlling the VCXO frequency within a
phase-locked loop (PLL), the output clock is phase and
frequency locked to the input clock. Through selection
of external loop filter components, the PLL loop
bandwidth and damping factor can be tailored to meet
system clock requirements. A loop bandwidth down to
the Hz range is possible.
ICS2059-02
Features
•
Excellent jitter attenuation for telecom and video
clocks
•
2:1 Input MUX for input reference clocks
•
No switching glitches on output
•
VCXO-based clock generation offers very low jitter
and phase noise generation
•
Output clock is phase and frequency locked to the
selected input reference clock
•
Fixed input to output phase relationship
•
+115 ppm minimum crystal frequency pullability
range, using recommended crystal
•
•
•
•
Industrial temperature range
Low power CMOS technology
16-pin TSSOP package
Single 3.3 V power supply
Block Diagram
Pullable Crystal
VDD
VDD
3
ISET
Input Clock ICLK2
Input Clock ICLK1
ISEL
X1
X2
1
0
Phase
Detector
Charge
Pump
VCXO
Selectable
Divider
CLK
SEL1:0
2
CHGP
VIN
GND
2
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CLOCK MULTIPLIER AND JITTER ATTENUATOR
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ICS2059-02
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CLOCK MULTIPLIER AND JITTER ATTENUATOR
VCXO AND SYNTHESIZERS
Pin Assignment
X1
VDD
VDD
VDD
VIN
GND
GND
CHGP
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
X2
ISEL
ICLK1
ICLK2
SEL0
CLK
SEL1
ISET
Output Frequency Select Table
Input
8 kHz
8 kHz
15.625 kHz
15.734265 kHz
151.875 kHz
27 MHz
SEL1 SEL0
0
0
1
1
M
M
0
1
0
1
0
1
N
1296
2430
1728
1716
128
1
Output Clock Crystal Used
(MHz)
(MHz)
10.368
20.736
19.44
19.44
27
27
27
27
19.44
19.44
27
27
16- pin ( 173 mil) TSSOP
Note: For SEL input pin programming:
0 = GND, 1 = VDD, M = Floating
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Pin
Name
X1
VDD
VDD
VDD
VIN
GND
GND
CHGP
ISET
SEL1
CLK
SEL0
ICLK2
ICLK1
ISEL
Pin
Type
—
Power
Power
Power
Input
Power
Power
Output
—
Input
Output
Input
Input
Input
Input
Pin Description
Crystal Input. Connect this pin to the specified crystal.
Power Supply. Connect to +3.3 V.
Power Supply. Connect to +3.3 V.
Power Supply. Connect to +3.3 V.
VCXO Control Voltage Input. Connect this pin to CHGP pin and the
external loop filter as shown in this data sheet.
Connect to ground.
Connect to ground.
Charge Pump Output. Connect this pin to the external loop filter and to
pin VIN.
Charge pump current setting node, connection for setting resistor.
Output Frequency Selection Pin 1. Determines output frequency as
per table above. Includes mid-level input.
Clock Output.
Output Frequency Selection Pin 0. Determines output frequency as
per table above. Internal pull-up resistor.
Input Clock Connection 2. Connect an input reference clock to this pin.
If unused, connect to ground.
Input Clock Connection 1. Connect an input reference clock to this pin.
If unused, connect to ground.
Input Selection. Used to select which reference input clock is active.
Low input level selects ICLK1, high input level selects ICLK2. Internal
pull-up resistor.
Crystal Output. Connect this pin to the specified crystal.
16
X2
—
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CLOCK MULTIPLIER AND JITTER ATTENUATOR
VCXO AND SYNTHESIZERS
Functional Description
The ICS2059-02 is a clock generator IC that generates
an output clock directly from an internal VCXO circuit
which works in conjunction with an external quartz
crystal. The VCXO is controlled by an internal PLL
(Phase-Locked Loop) circuit, enabling the device to
perform clock regeneration from an input reference
clock. The ICS2059-02 is configured to provide an
output clock that is the same frequency as the input
clock. There are 12 selectable input / output frequency
ranges, each of which is a submultiple of the supported
quartz crystal frequency range. Please refer to the
Output Clock Selection Table on Page 2.
Most typical PLL clock devices use an internal VCO
(Voltage Controlled Oscillator) for output clock
generation. By using a VCXO with an external crystal,
the ICS2059-02 is able to generate a low jitter, low
phase-noise output clock within a low bandwidth PLL.
This serves to provide input clock jitter attenuation and
enables stable operation with a low-frequency
reference clock.
The VCXO circuit requires an external pullable crystal
for operation. External loop filter components enable a
PLL configuration with low loop bandwidth.
generated due to the “fly-wheel” effect of the VCXO (the
quartz crystal is a high-Q tuned circuit). When the input
clocks are not phase aligned, the phase of the output
clock will change to reflect the phase of the newly
selected input at a controlled phase slope (rate of phase
change) as influenced by the PLL loop characteristics.
Quartz Crystal
It is important that the correct type of quartz crystal is
used with the ICS2059-02. Failure to do so may result
in reduced frequency pullability range, inability of the
loop to lock, or excessive output phase jitter.
The ICS2059-02 operates by phase-locking the VCXO
circuit to the input signal of the selected ICLK input. The
VCXO consists of the external crystal and the
integrated VCXO oscillator circuit. To achieve the best
performance and reliability, a crystal device with the
recommended parameters (shown below) must be
used, and the layout guidelines discussed in the PCB
Layout Recommendations section must be followed.
The frequency of oscillation of a quartz crystal is
determined by its cut and by the external load
capacitance. The ICS2059-02 incorporates variable
load capacitors on-chip which “pull”, or change, the
frequency of the crystal. The crystals specified for use
with the ICS2059-02 are designed to have zero
frequency error when the total of on-chip + stray
capacitance is 14 pF. To achieve this, the layout should
use short traces between the ICS2059-02 and the
crystal.
A complete description of the recommended crystal
parameters is in application note MAN05.
Application Information
Input / Output Frequency Configuration
The ICS2059-02 is configured to generate an output
frequency that is equal to the input reference frequency.
Clock frequencies that are supported are those which
fall into the ranges listed in the Output Clock Selection
Table on Page 2. Input bits SEL2:0 are set according to
this table, as is the external crystal frequency. Other
input/output frequency combinations can be used if the
necessary integer multiplication factor “N” appears in
the Output Frequency Select table. fro example, 20
MHz can be generated from 156.25 kHz by using select
M0, as N=128.
PLL Loop Filter Components
All analog PLL circuits use a loop filter to establish
operating stability. The ICS2059-02 uses external loop
filter components for the following reasons:
1) Larger loop filter capacitor values can be used,
allowing a lower loop bandwidth. This enables the use
of lower input clock reference frequencies and also
input clock jitter attenuation capabilities. Larger loop
filter capacitors also allow higher loop damping factors
when less passband peaking is desired.
2) The loop filter values can be user selected to
Input Mux
The Input Mux serves to select between two alternate
input reference clocks. Upon reselection of the input
clock, clock glitches on the output clock will not be
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VCXO AND SYNTHESIZERS
optimize loop response characteristics for a given
application.
Referencing the External Component Schematic on this
page, the external loop filter is made up of the
components R
Z
, C
1
and C
2
. R
SET
establishes PLL
charge pump current and therefore influences loop filter
characteristics.
External Component Schematic
C
L
(Refer to Crystal
Tuning section)
C
L
Crystal
X1
VDD
VDD
VDD
VIN
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
X2
ISEL
ICLK1
ICLK2
SEL0
CLK
SEL1
ISET
P
R
S
C
S
GND
GND
CHGP
16-pin (173 mil) TSSOP
R
SET
Recommended Loop Filter Values Vs. Output Frequency Range Selection
Crystal
SEL1 SEL0
Multiplier
(N)
0
0
2592
0
1
2430
1
0
1728
1
1
1716
M
0
128
M
1
1
R
SET
R
S
C
S
0.47
µF
0.68
µF
0.68
µF
0.68
µF
1
µF
1
µF
C
P
Loop
Bandwidth
(-3dB point)
Damping
Factor
3.00
2.97
3.17
3.18
3.16
3.08
180 kΩ
120 kΩ
330 kΩ
330 kΩ
120 kΩ
1 MΩ
820 kΩ
560 kΩ
680 kΩ
680 kΩ
330 kΩ
22 kΩ
1.8 nF
3.3 nF
3.9 nF
3.9 nF
3.3 nF
3.3 nF
11.2 Hz
11.8 Hz
11.5 Hz
11.5 Hz
14.5 Hz
204.2 Hz
Note: For SEL input pin programming: 0 = GND, 1 = VDD, M = Floating
IDT™ / ICS™
CLOCK MULTIPLIER AND JITTER ATTENUATOR
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ICS2059-02
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CLOCK MULTIPLIER AND JITTER ATTENUATOR
VCXO AND SYNTHESIZERS
A “normalized” PLL loop bandwidth may be calculated
as follows:
Charge Pump Current Table
R
S
×
I
CP
×
345
575
NBW
= -----------------------------------------
N
R
SET
1.4 MΩ
680 kΩ
540 kΩ
120 kΩ
Charge Pump Current
(I
CP
)
10
µA
20
µA
25
µA
100
µA
The “normalized” bandwidth equation above does not
take into account the effects of damping factor or the
second pole. However, it does provide a useful
approximation of filter performance.
The loop damping factor is calculated as follows:
Special considerations must be made in choosing loop
components C
S
and C
P.
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50Ω trace (a
commonly used trace impedance), place a 33Ω resistor
in series with the clock line, as close to the clock output
pin as possible. The nominal impedance of the clock
output is 20Ω (The optional series termination resistor
.
is not shown in the External Component Schematic.)
Damping Factor = R
S
×
375
×
I
CP
×
C
S
625
------------------------------------------
-
N
Where:
R
S
= Value of resistor in loop filter (Ohms)
I
CP
= Charge pump current (amps)
(refer to Charge Pump Current Table, below)
N = Crystal multiplier shown in the above
table
C
S
= Value of capacitor C
1
in loop filter (Farads)
As a general rule, the following relationship should be
maintained between components C
1
and C
2
in the loop
filter:
Decoupling Capacitors
As with any high-performance mixed-signal IC, the
ICS2059-02 must be isolated from system power
supply noise to perform optimally.
Decoupling capacitors of 0.01µF must be connected
between each VDD and the PCB ground plane. To
further guard against interfering system supply noise,
the ICS2059-02 should use one common connection to
the PCB power plane as shown in the diagram on the
next page. The ferrite bead and bulk capacitor help
reduce lower frequency noise in the supply that can
lead to output clock phase modulation.
C
P
S
=
-----
-
C
20
IDT™ / ICS™
CLOCK MULTIPLIER AND JITTER ATTENUATOR
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ICS2059-02
REV E 051310
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