MtronPTI reserves the right to make changes to the product(s) and service(s) described herein without notice. No liability is assumed as a result of their use or application.
Please see
www.mtronpti.com
for our complete offering and detailed datasheets. Contact us for your application specific requirements: MtronPTI
1-800-762-8800.
Rev: 10/14/2013
M630x Series
5x7 mm, 3.3/2.5/1.8 Volt, LVPECL/LVDS/CML/CMOS, TCXO/TCVCXO
Parameter
Frequency Range
Initial Accuracy
Frequency Stability
Frequency Vs. Aging
Frequency Vs. Supply Voltage
Frequency Vs. Reflow
Frequency Vs. Load
Operating Temperature
Storage Temperature
Operating Voltage
Symbol
F
R
F
I
∆F
T
/F
∆F
TIME
/F
∆F
VDD
/F
∆F
LOAD
/F
T
A
T
STG
V
CC
/V
S
/V
DD
Min.
Typ.
Max.
50
1400
50
135
-1
+1
See Ordering Information
-3
-1
±0.40
±0.75
±0.20
See Ordering Information
-55
3.135
2.375
1.71
3.3
2.5
1.8
+125
3.465
2.625
1.89
125
100
110
90
0.35
6
+3
+1
Units
MHz
MHz
ppm
ppm
ppm
ppm
ppm
ppm
ppm
°C
°C
V
V
V
mA
mA
mA
mA
ns
ns
V
% V
DD
V
% V
DD
V
%
%
%
Conditions/Notes
LVPECL, LVDS, CML (See Note 1)
CMOS
@ +25 °C
(Fmax - Fmin)/2 (See Note 2)
First year
Thereafter (per year)
5% voltage variation
2 reflows max.
5% supply voltage variation
Operating Current
I
CC
Rise/Fall Time
t
R
/t
F
V
OH
V
OL
V
CM
t
DC
1.2
45
45
45
0.7
±5
0.18
0.25
0.30
V
CC
- 1.02
90
Electrical Specifications
Logic “1” Level
Logic “0” Level
Common Mode Output Voltage
Symmetry (Duty Cycle)
V
CC
- 1.63
10
55
55
55
1.2
M6300
M6301
M6302
LVPECL
LVDS
CML
CMOS
LVPECL, LVDS, CML
CMOS
LVPECL
CMOS
LVPECL
CMOS
LVDS
@ 50% V
DD
(CMOS)
Output Voltage Level
Tuning Range
Voltage Control Range
0.95
V
C
Output Skew
Output Load
0.90
1.62
1.25
2.25
1.65
3.00
20
15
20
50 Ω to (V
CC
- 2)
V
DC
100 Ω Differential
15 pF
0.5
0.5
Enable/Disable Function
(Option B or G)
Enable/Disable Function
(Option S or M)
Phase Noise (Typical)
@ 622.080 MHz (LVPECL)
@ 100.000 MHz (HCMOS)
@ 50.000 MHZ (HCMOS)
80
80
10 Hz
-60
-70
-77
100 Hz
-90
-103
-109
1 kHz
-120
-123
-129
10 kHz
-127
-131
-137
@ 50% of waveform (LVPECL)
@ 1.25 V (LVDS)
V
pk-pk
CML
ppm VCTCXO only (See Note 3)
V
@ 1.8 V supply (VCTCXO only - Pad 2)
V
@ 2.5 V supply (VCTCXO only - Pad 2)
V
@ 3.3 V supply (VCTCXO only - Pad 2)
ps
LVPECL
ps
CML
ps
LVDS
LVPECL (See Note 4)
LVDS, CML (See Note 4)
CMOS (See Note 4)
%
Output Enabled
V
Output Disabled
V
Output Enabled
%
Output Disabled
100 kHz Offset from carrier
-133 dBc/Hz
-136 dBc/Hz
-141 dBc/Hz
Note
Note
Note
Note
Per MIL-STD-202, Method 213, Condition C
Shock
Per MIL-STD-202, Methods 201 & 204
Vibration
Per EIAJ-STD-002
Solderability
-8
Hermeticity
1 X 10 atm cc/sec of helium (Crystal only)
Per MIL-STD-883, Method 1011, Condition A
Thermal Shock
Per MIL-STD-883, Method 1010, Condition B
Thermal Cycle
1: Contact factory for frequencies over 945 MHz.
2: Contact factory for less than ±1 ppm frequency stability.
3: Contact factory for other tuning range options.
4: Refer to the load circuit diagram in this data sheet.
MtronPTI reserves the right to make changes to the product(s) and service(s) described herein without notice. No liability is assumed as a result of their use or application.
Environmental
Please see
www.mtronpti.com
for our complete offering and detailed datasheets. Contact us for your application specific requirements: MtronPTI
1-800-762-8800.
Load Circuit Diagrams
Lead Free Solder Profile
MtronPTI reserves the right to make changes to the product(s) and service(s) described herein without notice. No liability is assumed as a result of their use or application.
Please see
www.mtronpti.com
for our complete offering and detailed datasheets. Contact us for your application specific requirements: MtronPTI
Microchip MCU
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
