74LVC1G79
Single D-type flip-flop; positive-edge trigger
Rev. 11 — 2 July 2012
Product data sheet
1. General description
The 74LVC1G79 provides a single positive-edge triggered D-type flip-flop.
Information on the data input is transferred to the Q-output on the LOW-to-HIGH transition
of the clock pulse. The D-input must be stable one set-up time prior to the LOW-to-HIGH
clock transition for predictable operation.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this
device in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using I
OFF
. The I
OFF
circuitry disables the output, preventing the damaging backflow current through the device
when it is powered down.
2. Features and benefits
Wide supply voltage range from 1.65 V to 5.5 V
High noise immunity
Complies with JEDEC standard:
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8B/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
24
mA output drive (V
CC
= 3.0 V)
CMOS low power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Inputs accept voltages up to 5 V
Multiple package options
Specified from
40 C
to +85
C
and
40 C
to +125
C.
NXP Semiconductors
74LVC1G79
Single D-type flip-flop; positive-edge trigger
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74LVC1G79GW
74LVC1G79GV
74LVC1G79GM
74LVC1G79GF
74LVC1G79GN
74LVC1G79GS
74LVC1G79GX
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
Name
TSSOP5
SC-74A
XSON6
XSON6
XSON6
XSON6
X2SON5
Description
plastic thin shrink small outline package;
5 leads; body width 1.25 mm
plastic surface-mounted package; 5 leads
plastic extremely thin small outline package;
no leads; 6 terminals; body 1
1.45
0.5 mm
plastic extremely thin small outline package;
no leads; 6 terminals; body 1
1
0.5 mm
Version
SOT353-1
SOT753
SOT886
SOT891
Type number
extremely thin small outline package; no leads; SOT1115
6 terminals; body 0.9
1.0
0.35 mm
extremely thin small outline package; no leads; SOT1202
6 terminals; body 1.0
1.0
0.35 mm
X2SON5: plastic thermal enhanced extremely
thin small outline package; no leads; 5
terminals; body 0.8
0.8
0.35 mm
SOT1226
4. Marking
Table 2.
Marking codes
Marking
[1]
VP
V79
VP
VP
VP
VP
VP
Type number
74LVC1G79GW
74LVC1G79GV
74LVC1G79GM
74LVC1G79GF
74LVC1G79GN
74LVC1G79GS
74LVC1G79GX
[1]
The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
1
D
Q
4
1
4
D
CP
Q
2
CP
mna440
2
mna441
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
74LVC1G79
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 11 — 2 July 2012
2 of 21
NXP Semiconductors
74LVC1G79
Single D-type flip-flop; positive-edge trigger
CP
C
C
C
C
D
TG
C
TG
C
Q
C
C
TG
TG
C
C
mna442
Fig 3.
Logic diagram
6. Pinning information
6.1 Pinning
74LVC1G79
74LVC1G79
D
CP
1
2
GND
GND
3
001aaf188
D
5
V
CC
1
6
V
CC
CP
2
5
n.c.
3
4
Q
4
Q
001aaf189
Transparent top view
Fig 4.
Pin configuration SOT353-1 and SOT753
Fig 5.
Pin configuration SOT886
74LVC1G79
74LVC1G79
D
1
3
GND
CP
2
4
aaa-003029
5
V
CC
D
CP
GND
1
2
3
6
5
4
V
CC
n.c.
Q
Q
001aaf410
Transparent top view
Transparent top view
Fig 6.
Pin configuration SOT891, SOT1115 and
SOT1202
Fig 7.
Pin configuration SOT1226 (X2SON5)
74LVC1G79
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 11 — 2 July 2012
3 of 21
NXP Semiconductors
74LVC1G79
Single D-type flip-flop; positive-edge trigger
6.2 Pin description
Table 3.
Symbol
D
CP
GND
Q
n.c.
V
CC
Pin description
Pin
TSSOP5 and X2SON5 XSON6
1
2
3
4
-
5
1
2
3
4
5
6
data input
clock pulse input
ground (0 V)
data output
not connected
supply voltage
Description
7. Functional description
Table 4.
Input
CP
L
[1]
H = HIGH voltage level;
L = LOW voltage level;
= LOW-to-HIGH CP transition;
X = don’t care;
q = lower case letter indicates the state of referenced input, one set-up time prior to the LOW-to-HIGH CP transition.
Function table
[1]
Output
D
L
H
X
Q
L
H
q
74LVC1G79
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 11 — 2 July 2012
4 of 21
NXP Semiconductors
74LVC1G79
Single D-type flip-flop; positive-edge trigger
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
CC
I
GND
P
tot
T
stg
[1]
[2]
[3]
Parameter
supply voltage
input clamping current
input voltage
output clamping current
output voltage
output current
supply current
ground current
total power dissipation
storage temperature
Conditions
V
I
< 0 V
[1]
Min
0.5
50
0.5
-
[1][2]
[1][2]
Max
+6.5
-
+6.5
50
V
CC
+ 0.5
+6.5
50
100
-
250
+150
Unit
V
mA
V
mA
V
V
mA
mA
mA
mW
C
V
O
> V
CC
or V
O
< 0 V
Active mode
Power-down mode
V
O
= 0 V to V
CC
0.5
0.5
-
-
100
T
amb
=
40 C
to +125
C
[3]
-
65
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
When V
CC
= 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.
For TSSOP5 and SC-74A packages: above 87.5
C
the value of P
tot
derates linearly with 4.0 mW/K.
For XSON6 and X2SON5 packages: above 118
C
the value of P
tot
derates linearly with 7.8 mW/K.
9. Recommended operating conditions
Table 6.
Symbol
V
CC
V
I
V
O
T
amb
t/V
Recommended operating conditions
Parameter
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate
V
CC
= 1.65 V to 2.7 V
V
CC
= 2.7 V to 5.5 V
Active mode
V
CC
= 0 V; Power-down mode
Conditions
Min
1.65
0
0
0
40
-
-
Typ
-
-
-
-
-
-
-
Max
5.5
5.5
V
CC
5.5
+125
20
10
Unit
V
V
V
V
C
ns/V
ns/V
74LVC1G79
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 11 — 2 July 2012
5 of 21
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