ESR
Ultra-low ESR “U” Range
“U” range of Ultra-low ESR Capacitors
Electrical Details
Capacitance Range
0.5pF to 240pF
Temperature Coefficient of Capacitance (TCC) 0 ± 30ppm/˚C
Q factor
Insulation Resistance (IR)
Dielectric Withstand Voltage (DWV)
Ageing Rate
>2000 @ 1MHz
100GΩ or 1000secs (whichever is the less)
Voltage applied for 5 ±1 seconds, 50mA
charging current maximum
Zero
The Ultra-low ESR “U” range offers a very stable, High Q material system
that provides excellent low loss performance in systems below 3GHz.
Optimised for lowest possible ESR, this range of high frequency capacitors
is suitable for many applications where economical, high performance is
required.
Minimum/Maximum Capacitance Values – “U” range of Ultra-low ESR Capacitors
Chip Size
Min Cap
200V/250V
Tape Quantities
0603
0.1pF
100pF
7” reel – 4,000
13” reel – 16,000
0805
0.2pF
240pF
7” reel – 3,000
13” reel – 12,000
Size
Length
(L1)
1.6 ± 0.2
Width
(W)
0.8 ± 0.2
Thickness
(T)
0.8 Max
Band
(L2)
0.10 – 0.40
0603
0805
2.0 ± 0.3
1.25 ± 0.2
1.3 Max
0.13 – 0.75
Ordering Information – Ultra-low ESR “U” Range
0805
Chip Size
0603
0805
J
Termination
J
= Silver base with
nickel barrier (100%
matte tin plating).
RoHS compliant
A
= Silver base with
nickel barrier (tin/lead
plating with min. 10%
lead).
Not RoHS compliant
250
Voltage d.c.
(marking code)
250
= 250V
0101
Capacitance in Pico
farads (pF)
<1.0pF
Insert a P for the decimal
point as the first character.
e.g.,
P300
= 0.3pF
Values in 0.1pF steps
≥1.0pF & <10pF
Insert a P for the decimal
point as the second
character.
e.g.,
8P20
= 8.2pF
Values are E24 series
≥10pF
First digit is 0.
Second and third digits are
significant figures of
capacitance code.
The fourth digit is the
number of zeros following.
e.g.,
0101
= 100 pF
Values are E24 series
<10pF
B:
± 0.10pF
C:
± 0.25pF
D:
± 0.5pF
≥10pF
F:
± 1%
G:
± 2%
J:
± 5%
K:
± 10%
J
Capacitance
Tolerance
<4.7pF
H:
± 0.05pF
B:
± 0.10pF
C:
± 0.25pF
D:
± 0.5pF
U
Dielectric
U =
Ultra-low ESR
“U” range
T
Packaging
T
= 178mm
(7”) reel
R
= 330mm
(13”) reel
B
= Bulk pack
– tubs or trays
© Knowles 2015
ESRDatasheet Issue 7 (P110711) Release Date 27/11/15
Page 1 of 11
Tel: +44 1603 723300 | Email SyferSales@knowles.com | www.knowlescapacitors.com/syfer
Typical Performance Curves
0603
The 0603 “U” range has been modelled by Modelithics Inc. (www.modelithics.com) and scaleable models are available as part of
their model libraries for Keysight ADS, Keysight GENESYS, and AWR Microwave Office EDA software.
S parameters for the 0603 are available on both the Modelithics (www.modelithics.com) and Knowles Capacitors website
www.knowlescapacitors.com/syfer
© Knowles 2015
ESRDatasheet Issue 7 (P110711) Release Date 27/11/15
Page 2 of 11
Tel: +44 1603 723300 | Email SyferSales@knowles.com | www.knowlescapacitors.com/syfer
0805
Note curves are typical, based on data measured using a Boonton 34A resonant tube and Keysight E4991 impedance analyser
with Keysight 16197A test fixture
Actual performance in circuit may differ and parts should be tested in application.
© Knowles 2015
ESRDatasheet Issue 7 (P110711) Release Date 27/11/15
Page 3 of 11
Tel: +44 1603 723300 | Email SyferSales@knowles.com | www.knowlescapacitors.com/syfer
Performance
Lot by lot inspection (all batches)
Additional
Requirements
Inspect
construction and
workmanship
Verify physical
dimensions comply
with Table 1
Class I
1MHz @ 1.0V
Sample
Size
125
Test
Accept/Fail
MIL-STD-883
Method 2009
Test Method
10x magnification.
Free of visual defects
Digital Vernier or
micrometer as
applicable.
Within specified
tolerance
Within specified
tolerance
Visual inspection
0/1
Dimensions
13
0/1
JESD22
Method JB-100
Capacitance
100%
N/a
CECC 32 100
Clause 4.6.1
D.F.
Class I
1MHz @ 1.0V
100%
N/a
CECC 32 100
Clause 4.6.2
<0.0005 @ 1MHz
(Q > 2000 @ 1MHz)
No breakdown or
flashover. R≥ 100MΩ or
1s, whichever is the
smaller
100GΩ or 1000secs
(whichever is the less)
Cut in both directions.
Inspect and measure as
applicable.
Free from internal
defects
Dip and look method.
>95% coverage
Voltage Proof
VP = 500V
100%
N/a
CECC 32 100
Clause 4.6.4
I.R.
R
V
> 100V IR
Voltage = 100V
100%
N/a
CECC 32 100
Clause 4.6.3
D.P.A.
-
29
0/1
EIA-469
Solderability
-
Carried out for
each
manufacturing
batch of dielectric
material
10
0/1
IEC 60068-2-58
Test Td
Temperature
Characteristic of
Capacitance
-
-
CECC 32 100
Clause 4.7.2
X7R TC ±15% over -
55ºC / +125ºC, no volts
applied
© Knowles 2015
ESRDatasheet Issue 7 (P110711) Release Date 27/11/15
Page 4 of 11
Tel: +44 1603 723300 | Email SyferSales@knowles.com | www.knowlescapacitors.com/syfer
Performance
Periodic Tests conducted on randomly selected batches
Test
High Temperature Exposure
(Storage)
Additional Requirements
Un-powered. 1000 hours @ T=150
o
C.
Measurement at 24 ± 2 hours after test
conclusion
1000 cycles -55
o
C to +125
o
C
Measurement at 24 ± 2 hours after test
conclusion
T = 24 hours/cycle. Note: Steps 7a & 7b
not required. Un-powered.
Measurement at 24 ± 2 hours after test
conclusion
1000 hours 85
o
C/85%RH. Applied
voltage 50V and 1.5V
Measurement at 24 ± 2 hours after test
conclusion
Condition D Steady State T
A
=125
o
C at
1.5 x R
V
.
Measurement at 24 ± 2 hours after test
conclusion
Figure 1 of Method 213. Condition F
5g’s for 20 minutes, 12 cycles each of 3
orientations. Note: Use 8”X5” PCB .031”
thick 7 secure points on one long side
and 2 secure points at corners of
opposite sides. Parts mounted within 2”
from any secure point. Test from 10-
2000Hz
MIL-STD-202
Method 108
Test Method
Un-mounted.
Post test measure at room
temperature within 24 ± 2 hours
Mounted on standard test boards.
5mins soak at extremes Post test
measure at room temperature
within 24 ± 2 hours
Preconditioning at 50°C for 24
hrs followed by 10 cycles of 25°C
to 65°C at 95%RH.
Post test measure at room
temperature within 24 ± 2 hours
Mounted on test boards.
Post test measure at room
temperature within 24 ± 2 hours
Mounted on test leads
Post test measure at room
temperature within 24 ± 2 hours
3x half sine shock pulses of 1.5kg
peak.
Temperature Cycling
JESD22
Method JA-104
Moisture Resistance
MIL-STD-202
Method 106
Biased Humidity
MIL-STD-202
Method 103
Operational Life
MIL-STD-202
Method 108
MIL-STD-202
Method 213
Mechanical Shock
Vibration
MIL-STD-202
Method 204
Post test measure at room
temperature within 24 ± 2 hours
Resistance to Soldering Heat
Condition B, no pre-heat of samples:
Single Wave Solder – Procedure 2
MIL-STD-202
Method 210
Samples subjected to solder dip
at 260°C for 10±1s. Immersion
and emersion rates =
25±6mm/s.
Mounted on test boards.
Post test measure at room
temperature within 24 ± 2 hours
Thermal Shock
-55
o
C/+125
o
C. Number of cycles 300.
Maximum transfer time – 20 seconds,
Dwell time – 15 minutes. Air-Air
MIL-STD-202
Method 107
Board Flex
3mm deflection Class I
AEC-Q200-005
Bend test substrate with the
capacitor for 60s+5s.
Terminal Strength
Force of 1.0kg (0603) or 1.8kg (0805)
for 60 seconds
AEC-Q200-006
Mounted on test substrate. Force
applied to side of component by
calibrated load cell.
Post test measure at room
temperature within 24 ± 2 hours
and visual
Mounted on test boards. Tested
within 15mins of removal from
chamber.
Final measurements after 1 to
2hrs recovery time
Damp Heat Steady State
56 days, 40ºC/ 93%RH. 15 x no volts,
15 x 5Vdc, 15 x 50V
BS EN132100
Clause 4.14
© Knowles 2015
ESRDatasheet Issue 7 (P110711) Release Date 27/11/15
Page 5 of 11
Tel: +44 1603 723300 | Email SyferSales@knowles.com | www.knowlescapacitors.com/syfer
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