19-2905; Rev 1; 3/09
KIT
ATION
EVALU
E
BL
AVAILA
12.5Gbps CML 2
×
2 Crosspoint Switch
General Description
The MAX3841 is a low-power, 12.5Gbps 2
×
2 cross-
point switch IC for high-speed serial data loopback,
redundancy, and switching applications. The MAX3841
current-mode logic (CML) inputs and outputs have iso-
lated V
CC
connections to enable DC-coupled interfaces
to 1.8V, 2.5V, or 3.3V CML ICs. Fully differential signal
paths and Maxim’s second-generation SiGe technology
provide optimum signal integrity, minimizing jitter,
crosstalk, and signal skew. The MAX3841 is ideal for
serial OC-192 and 10GbE optical module, line card,
switch fabric, and similar applications.
The MAX3841 has 150mV
P-P
minimum differential input
sensitivity, and 500mV
P-P
nominal differential output
swing. Unused outputs can be powered down individu-
ally to conserve power. In addition to functioning as a 2
×
2 switch, the MAX3841 can be configured as a 2:1
multiplexer, 1:2 buffer, or dual 1:1 buffer. The MAX3841
is available in a 4mm
×
4mm 24-pin thin QFN package,
and consumes only 215mW with both outputs enabled.
♦
Up to 12.5Gbps Operation
♦
Less Than 10ps
P-P
Deterministic Jitter
♦
Less Than 0.7ps
RMS
Random Jitter
♦
1.8V, 2.5V, and 3.3V DC-Coupled CML I/O
♦
Independent Output Power-Down
♦
4mm
×
4mm Thin QFN Package
♦
-40°C to +85°C Operation
♦
+3.3V Core Supply
♦
215mW Power Consumption (Excluding
Termination Currents)
Features
MAX3841
Ordering Information
PART
MAX3841ETG
MAX3841ETG+
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
24 Thin QFN-EP*
24 Thin QFN-EP*
Applications
OC-192, 10GbE Switch/Line Cards
OC-192, 10GbE Optical Modules
System Redundancy/Self Test
Clock Fanout
+Denotes
a lead(Pb)-free/RoHS-compliant package.
*EP
= Exposed pad.
Pin Configuration appears at end of data sheet.
Typical Application Circuit
1.8V
2.5V
3.3V
2.5V
VCC1OUT
SDI+
10Gbps
SERIAL
OPTICAL
MODULE
SDI-
SDO+
SDO-
2.5V
VCC1IN
SEL1 SEL2
ENO1
ENO2
VCC2OUT
GND
OUT1+
OUT1-
IN1+
IN1-
MAX3841
V
CC
VCC2IN
IN2+
IN2-
OUT2+
OUT2-
1.8V
3.3V
1.8V
10Gbps
CDR/SERDES
ASIC
SDO+
SDO-
SDI+
SDI-
LOOPBACK
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim's website at www.maxim-ic.com.
12.5Gbps CML 2
×
2 Crosspoint Switch
MAX3841
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
CC
..............................................-0.5V to +4.0V
CML Supply Voltage (VCC_IN, VCC_OUT)...........-0.5V to +4.0V
Continuous Output Current (OUT1±, OUT2±)...................±25mA
CML Input Voltage (IN1±, IN2±)...........-0.5V to (VCC_IN + 0.5V)
LVCMOS Input Voltage (SEL1, SEL2,
ENO1, ENO2) .........................................-0.5V to (V
CC
+ 0.5V)
Continuous Power Dissipation (T
A
= +85°C)
24-Pin Thin QFN (derate 20.8mW/°C
above +85°C).............................................................1352mW
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-55°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
CC
= +3.0V to +3.6V, VCC_IN = +1.71V to V
CC
, VCC_OUT = +1.71V to V
CC
, T
A
= -40°C to +85°C. Typical values are at V
CC
=
+3.3V, VCC_IN = VCC_OUT = 1.8V, T
A
= +25°C, unless otherwise noted.)
PARAMETER
Core Supply Current
Data Rate
CML Input Differential
CML Input Common Mode
CML Input Termination
CML Input Return Loss
CML Output Differential
CML Output Termination
CML Output Transition Time
Deterministic Jitter
Random Jitter
Propagation Delay
Channel-to-Channel Skew
Output Duty-Cycle Skew
LVCMOS Input Current
LVCMOS Input High Voltage
LVCMOS Input Low Voltage
I
IH
, I
IL
V
IH
V
IL
t
R
, t
F
V
OUT
V
IN
SYMBOL
I
CC
(Note 1)
AC-coupled or DC-coupled (Note 2)
DC-coupled
Single ended
Up to 10GHz
(Note 2)
Single ended
20% to 80% (Notes 1, 3)
(Notes 1, 4)
V
IN
= 150mV
P-P
(Notes 1, 5)
Any input to output (Note 1)
(Note 1)
50% input duty cycle (Notes 1, 3)
-10
1.7
0.7
0.3
100
400
42.5
CONDITIONS
Excluding CML termination currents
0
150
VCC_IN - 0.3
42.5
50
12
500
50
600
57.5
30
10
0.7
140
12
8
+10
ps
ps
P-P
ps
RMS
ps
ps
ps
μA
V
V
MIN
TYP
65
MAX
90
12.5
1200
VCC_IN
57.5
dB
mV
P-P
UNITS
mA
Gbps
mV
P-P
V
Note 1:
Note 2:
Note 3:
Note 4:
Guaranteed by design and characterization.
Differential swing is defined as V
IN
= (IN_+) - (IN_-) and V
OUT
= (OUT_+) - (OUT_-). See Figure 1.
Measured using a 0000011111 pattern at 12.5Gbps, and V
IN
= 400mV
P-P
differential.
Measured at 9.953Gbps using a pattern of 100 ones, 2
7
- 1 PRBS, 100 zeros, 2
7
- 1 PRBS, and at 12.5Gbps using a ±K28.5
pattern. VCC_IN = VCC_OUT = 1.8V, and V
IN
= 400mV
P-P
differential.
Note 5:
Refer to Application Note 1181:
HFAN-04.5.1: Measuring Random Jitter on a Digital Sampling Oscilloscope.
2
_______________________________________________________________________________________
12.5Gbps CML 2
×
2 Crosspoint Switch
Typical Operating Characteristics
(V
CC
= 3.3V, VCC_IN, VCC_OUT = 1.8V, V
IN
= 500mV
P-P
, T
A
= +25°C, unless otherwise noted.)
MAX3841
CORE SUPPLY CURRENT vs. TEMPERATURE
(EXCLUDES CML I/O CURRENTS)
MAX3841 toc01
SUPPLY CURRENT vs. TEMPERATURE
(CORE PLUS CML I/O CURRENTS)
130
120
SUPPLY CURRENT (mA)
110
100
90
80
70
60
50
40
CML INPUTS AND OUTPUTS AC-COUPLED
-40
-15
10
35
60
85
0 OUTPUTS ENABLE
60mV/div
2 OUTPUTS ENABLE
1 OUTPUT ENABLE
MAX3841 toc02
OUTPUT EYE DIAGRAM
(12.5Gbps, 2
23
- 1 PRBS)
MAX3841 toc03
140
130
120
SUPPLY CURRENT (mA)
110
100
90
80
70
60
50
40
-40
-15
10
35
60
2 OUTPUTS ENABLE
0 OUTPUTS ENABLE
1 OUTPUT ENABLE
140
85
14ps/div
TEMPERATURE (°C)
TEMPERATURE (°C)
OUTPUT EYE DIAGRAM
(10.7Gbps, 2
23
- 1 PRBS)
MAX3841 toc04
OUTPUT EYE DIAGRAM
(6.25Gbps, 2
23
- 1 PRBS)
MAX3841 toc05
OUTPUT EYE DIAGRAM
(622Mbps, 2
23
- 1 PRBS)
MAX3841 toc06
60mV/div
60mV/div
60mV/div
16ps/div
28ps/div
270ps/div
DETERMINISTIC JITTER
vs. TEMPERATURE
14
DETERMINISTIC JITTER (ps)
12
10
8
6
4
2
0
-40
-15
10
35
60
85
TEMPERATURE (°C)
±K28.5
AT 12.5Gbps
2
7
- 1 PRBS + 100CIDs
AT 10.7Gbps
MAX3841 toc07
DIFFERENTIAL OUTPUT SWING
vs. TEMPERATURE
540
DIFFERENTIAL OUTPUT (mV
P-P
)
530
520
510
500
490
480
470
460
450
-40
-15
10
35
60
85
OUT1
MAX3841 toc08
PROPAGATION DELAY
MAX3841 toc09
16
550
IN1
100ps/div
TEMPERATURE (°C)
_______________________________________________________________________________________
3
12.5Gbps CML 2
×
2 Crosspoint Switch
MAX3841
Pin Description
PIN
1, 12
2, 5
3
4
6
7
8, 11
9
10
13, 24
14, 17
15
16
18
19
20, 23
21
22
—
NAME
V
CC
VCC1IN
IN1+
IN1-
SEL1
SEL2
VCC2IN
IN2+
IN2-
GND
VCC1OUT
OUT1-
OUT1+
ENO1
ENO2
VCC2OUT
OUT2-
OUT2+
EP
+3.3V Core Supply Voltage
Supply Voltage for CML Input IN1. Connect to 1.8V, 2.5V, or 3.3V.
Positive Serial Data Input 1, CML
Negative Serial Data Input 1, CML
Output 1 Select, LVCMOS Input. See Table 1.
Output 2 Select, LVCMOS Input. See Table 1.
Supply Voltage for CML Input IN2. Connect to 1.8V, 2.5V, or 3.3V.
Positive Serial Data Input 2, CML
Negative Serial Data Input 2, CML
Supply Ground
Supply Voltage for CML Output OUT1. Connect to 1.8V, 2.5V, or 3.3V.
Negative Serial Data Output 1, CML
Positive Serial Data Output 1, CML
Output 1 Enable, LVCMOS Input. See Table 1.
Output 2 Enable, LVCMOS Input. See Table 1.
Supply Voltage for CML Output OUT2. Connect to 1.8V, 2.5V, or 3.3V.
Negative Serial Data Output 2, CML
Positive Serial Data Output 2, CML
Exposed Pad. The exposed pad must be soldered to the circuit board ground for proper thermal and
electrical performance.
FUNCTION
Detailed Description
The MAX3841 contains a pair of CML inputs that drive
two 2:1 multiplexers, with separate select inputs SEL1
and SEL2, providing a 2
×
2 crosspoint data path. The
outputs of the multiplexers each drive a high-perfor-
mance CML output that can be disabled (powered
down) using the ENO1/ENO2 inputs. All of the data
paths are fully differential to minimize jitter, crosstalk,
and signal skew. See Figure 1 for the functional diagram.
The CML inputs accept serial NRZ data with differential
amplitude from 150mV
P-P
to 1200mV
P-P
(see Figure 2).
The CML outputs provide 500mV
P-P
nominal differential
swing, resulting in low power consumption.
2
IN1
CML
1
CML
0
ENO1
2
IN2
CML
1
CML
0
ENO2
2
OUT2
SEL1
2
OUT1
CML Input and Output Buffers
The MAX3841 input and output buffers are terminated
with 50Ω to independent supply lines, and are also com-
patible with 100Ω differential terminations. (See Figures 3
and 4.) Separate power-supply connections are provided
for the core, input buffers, and output buffers to allow DC-
coupling to 1.8V, 2.5V, or 3.3V CML ICs. If desired, the
CML inputs and outputs can be AC-coupled.
MAX3841
SEL2
Figure 1. Functional Diagram
4
_______________________________________________________________________________________
12.5Gbps CML 2
×
2 Crosspoint Switch
MAX3841
V-
600mV
MAX
V+
Table 1. Output Controls
75mV
MIN
ENO1
0
0
0
0
1
ENO2
0
0
0
0
1
SEL1
0
0
1
1
X
SEL2
0
1
0
1
X
OUT1
IN2
IN2
IN1
IN1
Disabled
OUT2
IN1
IN2
IN1
IN2
Disabled
150mV
MIN
(V+) - (V-)
1200mV
MAX
Applications Information
Select and Enable Controls
The MAX3841 provides two LVCMOS-compatible
select inputs, SEL1 and SEL2. Either data input can be
connected to either or both data outputs. The MAX3841
provides two LVCMOS-compatible enable inputs,
ENO1 and ENO2, so each output can be disabled
independently. The MAX3841 can also be used as a
1:2 driver, 2:1 multiplexer, or a dual 1:1 buffer by using
the LVCMOS control inputs accordingly (see Table 1).
Figure 2. Definition of Differential Voltage Swing
VCC_IN
50Ω
IN_+
50Ω
Power-Supply Connections
Each of the input and output power-supply connections
(VCC1IN, VCC2IN, VCC1OUT, VCC2OUT) is indepen-
dent and need not be connected to the same voltage.
The input and output supplies can be connected to
1.8V, 2.5V, or 3.3V, but the core supply (V
CC
) must be
connected to 3.3V for proper operation.
IN_-
MAX3841
Input and Output Interfaces
Figure 3. Equivalent CML Input Circuit
VCC_OUT
50Ω
50Ω
OUT_+
OUT_-
The MAX3841 inputs and outputs can be AC-coupled
or DC-coupled according to the application. If an input
or output is not used it should be terminated with 50Ω
to the correct input or output supply voltage. For more
information about interfacing with logic families, refer to
Application Note 291:
HFAN-01.0: Introduction to
LVDS, PECL, and CML.
The MAX3841 is packaged in a 4mm
×
4mm 24-pin thin
QFN with exposed pad. The exposed pad provides
thermal and electrical connectivity to the IC and must
be soldered to a high-frequency ground plane. Use
multiple vias to connect the exposed pad underneath
the package to the PC board ground plane.
Use good layout techniques for the 10Gbps PC board
transmission lines, and configure the layout near the IC to
minimize impedance discontinuities. Power-supply
decoupling capacitors should be located as close as
possible to the IC.
Package and Layout Considerations
MAX3841
Figure 4. Equivalent CML Output Circuit
_______________________________________________________________________________________
5
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