HIGH SPEED 3.3V
2K X 8 DUAL-PORT
STATIC RAM WITH
INTERRUPTS
Features
◆
IDT71V321S/L
IDT71V421S/L
◆
◆
◆
High-speed access
– Commercial: 25/35/55ns (max.)
– Industrial: 25ns (max.)
Low-power operation
– IDT71V321/IDT71V421S
—
Active: 325mW (typ.)
—
Standby: 5mW (typ.)
– IDT71V321/V421L
—
Active: 325mW (typ.)
—
Standby: 1mW (typ.)
Two
INT
flags for port-to-port communications
MASTER IDT71V321 easily expands data bus width to 16-
or-more-bits using SLAVE IDT71V421
◆
◆
◆
◆
◆
◆
◆
◆
On-chip port arbitration logic (IDT71V321 only)
BUSY
output flag on IDT71V321;
BUSY
input on IDT71V421
Fully asynchronous operation from either port
Battery backup operation—2V data retention (L only)
TTL-compatible, single 3.3V power supply
Available in 52-pin PLCC, 64-pin TQFP and STQFP
packages
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Green parts available, see ordering information
Functional Block Diagram
OE
L
CE
L
R/W
L
OE
R
CE
R
R/W
R
I/O
0L
- I/O
7L
I/O
Control
BUSY
L
(1,2)
I/O
0R
-I/O
7R
I/O
Control
BUSY
R
A
10R
A
0R
(1,2)
A
10L
A
0L
Address
Decoder
11
MEMORY
ARRAY
11
Address
Decoder
CE
L
OE
L
R/W
L
ARBITRATION
and
INTERRUPT
LOGIC
CE
R
OE
R
R/W
R
INT
L
(2)
INT
R
3026 drw 01
(2)
NOTES:
1. IDT71V321 (MASTER):
BUSY
is an output. IDT71V421 (SLAVE):
BUSY
is input.
2.
BUSY
and
INT
are totem-pole outputs.
JANUARY 2010
1
©2010 Integrated Device Technology, Inc.
DSC-3026/11
IDT71V321/71V421S/L
High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Description
The IDT71V321/IDT71V421 are high-speed 2K x 8 Dual-Port
Static RAMs with internal interrupt logic for interprocessor communica-
tions. The IDT71V321 is designed to be used as a stand-alone 8-bit
Dual-Port RAM or as a "MASTER" Dual-Port RAM together with the
IDT71V421 "SLAVE" Dual-Port in 16-or-more-bit memory system ap-
plications results in full speed, error-free operation without the need for
additional discrete logic.
The device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access
for reads or writes to any location in memory. An automatic power
down feature, controlled by
CE,
permits the on chip circuitry of each
port to enter a very low standby power mode.
Fabricated using IDT's CMOS high-performance technology, these
devices typically operate on only 325mW of power. Low-power (L)
versions offer battery backup data retention capability, with each Dual-
Port typically consuming 200µW from a 2V battery.
The IDT71V321/IDT71V421 devices are packaged in a 52-pin
PLCC, a 64-pin TQFP (thin quad flatpack), and a 64-pin STQFP
(super thin quad flatpack).
Pin Configurations
(1,2,3)
INDEX
A
1L
A
2L
A
3L
A
4L
A
5L
A
6L
A
7L
A
8L
A
9L
I/O
0L
I/O
1L
I/O
2L
I/O
3L
87 6 5 4 3 2 1 52 51 50 49 48 47
46
45
9
44
10
43
11
42
12
IDT71V321/421J
41
13
J52-1
(4)
40
14
52-Pin PLCC
39
15
Top View
(5)
38
16
37
17
36
18
35
19
20
34
21 22 23 24 25 26 27 28 29 30 31 32 33
R/W
R
BUSY
R
INT
R
A
10R
OE
R
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
A
7R
A
8R
A
9R
NC
I/O
7R
,
3026 drw 02
INT
L
BUSY
L
R/W
L
CE
L
A
0L
OE
L
A
10L
I/O
4L
I/O
5L
I/O
6L
I/O
7L
NC
GND
I/O
0R
I/O
1R
I/O
2R
I/O
3R
I/O
4R
I/O
5R
I/O
6R
V
CC
CE
R
INDEX
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
N/C
N/C
A
10L
INT
L
BUSY
L
R/W
L
CE
L
V
CC
V
CC
CE
R
R/W
R
BUSY
R
INT
R
A
10R
N/C
N/C
NOTES:
1. All V
CC
pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. J52-1 package body is approximately .75 in x .75 in x .17 in.
PP64-1 package body is approximately 10mm x 10mm x 1.4mm.
PN64-1 package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
OE
L
A
0L
A
1L
A
2L
A
3L
A
4L
A
5L
A
6L
N/C
A
7L
A
8L
A
9L
N/C
I/O
0L
I/O
1L
I/O
2L
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
IDT71V321/421PF or TF
PP64-1
(4)
&
PN64-1
(4)
64-Pin STQFP
64-Pin TQFP
Top View
(5)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
OE
R
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
N/C
A
7R
A
8R
A
9R
N/C
N/C
I/O
7R
I/O
6R
I/O
3L
N/C
I/O
4L
I/O
5L
I/O
6L
I/O
7L
N/C
GND
GND
I/O
0R
I/O
1R
I/O
2R
I/O
3R
N/C
I/O
4R
I/O
5R
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
3026 drw 03
2
6.42
IDT71V321/71V421S/L
High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Absolute Maximum Ratings
(1)
Symbol
V
TERM
(2)
Rating
Terminal Voltage
with Respect
to GND
Operating
Temperature
Temperature
Under Bias
Storage
Temperature
DC Output
Current
Commercial
& Industrial
-0.5 to +4.6
Unit
V
Recommended Operating
Temperature and Supply Voltage
(1,2)
Grade
Commercial
Industrial
Ambient
Temperature
0
O
C to +70
O
C
-40
O
C to +85
O
C
GND
0V
0V
Vcc
3.3V
+
0.3V
3.3V
+
0.3V
3026 tbl 02
T
A
T
BIAS
T
STG
I
OUT
0 to +70
-55 to +125
-65 to +150
50
°C
o
C
C
o
NOTES:
1. This is the parameter T
A
. This is the "instant on" case temperature.
2. Industrial temperature: for specific speeds, packages and powers contact your
sales office.
mA
3026 tbl 01
Recommended DC Operating
Conditions
Symbol
V
CC
GND
V
IH
V
IL
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Min.
3.0
0
2.0
-0.3
(1)
Typ.
3.3
0
____
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of the specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. V
TERM
must not exceed V
CC
+ 10% for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of V
TERM
> V
CC
+ 10%.
Max.
3.6
0
V
CC
+0.3
(2)
0.8
Unit
V
V
V
V
3026 tbl 03
____
Capacitance
(1)
Symbol
C
IN
C
OUT
NOTES:
1. V
IL
(min.) = -1.5V for pulse width less than 20ns.
2. V
TERM
must not exceed Vcc + 0.3V.
(TA = +25°C, f = 1.0MHz) TQFP Only
Parameter
Input Capacitance
Output Capacitance
Conditions
(2)
V
IN
= 3dV
V
OUT
= 3dV
Max.
9
10
Unit
pF
pF
3026 tbl 04
NOTES:
1. This parameter is determined by device characterization but is not production
tested.
2. 3dv references the interpolated capacitance when the input and output signals
switch from 0V to 3V or from 3V to 0V.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(V
CC
= 3.3V ± 0.3V)
71V321S
71V421S
Symbol
|I
LI
|
|I
LO
|
V
OL
V
OH
Parameter
Input Leakage Current
(1)
Output Leakage Current
Output Low Voltage
Output High Voltage
Test Conditions
V
CC
= 3.6V,
V
IN
= 0V to V
CC
CE
= V
IH
, V
OUT
= 0V to V
CC
V
CC
= 3.6V
I
OL
= 4mA
I
OH
= -4mA
Min.
___
71V321L
71V421L
Min.
___
Max.
10
10
0.4
___
Max.
5
5
0.4
___
Unit
µA
µA
V
V
3026 tbl 05
___
___
___
___
2.4
2.4
NOTE:
1. At V
CC
< 2.0V input leakages are undefined.
3
6.42
IDT71V321/71V421S/L
High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(1,2)
(V
CC
= 3.3V ± 0.3V)
71V321X25
71V421X25
Com'l & Ind
Symbol
I
CC
Parameter
Dynamic Operating
Current
(Both Ports Active)
Standby Current
(Both Ports - TTL
Level Inputs)
Standby Current
(One Port - TTL
Level Inputs)
Full Standby Current
(Both Ports - All
CMOS Level Inputs)
Test Condition
CE
= V
IL
, Outputs Disabled
SEM
= V
IH
f = f
MAX
(3)
CE
R
=
CE
L
= V
IH
SEM
R
=
SEM
L
= V
IH
f = f
MAX
(3)
CE
"A"
= V
IL
and
CE
"B"
= V
IH
(5)
Active Port Outputs Disabled,
f=f
MAX
(3)
SEM
R
=
SEM
L
= V
IH
Both Ports
CE
L
and
CE
R
> V
CC
- 0.2V
V
IN
> V
CC
- 0.2V or
V
IN
< 0.2V, f = 0
(4)
SEM
R
=
SEM
L
> V
CC
- 0.2V
CE
"A"
< 0.2V and
CE
"B"
> V
CC
- 0.2V
(5)
SEM
R
=
SEM
L
> V
CC
- 0.2V
V
IN
> V
CC
- 0.2V or V
IN
< 0.2V
Active Port Outputs Disabled
f = f
MAX
(3)
Version
COM'L
IND
COM'L
IND
COM'L
IND
COM'L
S
L
L
S
L
L
S
L
L
S
L
L
S
L
L
Typ.
55
55
55
15
15
15
25
25
25
1.0
0.2
0.2
25
25
25
Max.
130
100
130
35
20
35
75
55
75
5
3
6
70
55
70
71V321X35
71V421X35
Com'l & Ind
Typ.
55
55
55
15
15
15
25
25
25
1.0
0.2
1.0
25
25
25
Max.
125
95
125
35
20
35
70
50
70
5
3
5
65
50
65
71V321X55
71V421X55
Typ.
55
55
___
Max.
115
85
___
Unit
mA
I
SB1
15
15
___
35
20
___
mA
I
SB2
25
25
___
60
40
___
mA
I
SB3
1.0
0.2
___
5
3
___
mA
IND
COM'L
I
SB4
Full Standby Current
(One Port - All
CMOS Level Inputs)
25
25
___
55
40
___
mA
IND
3026 tbl 06
NOTES:
1. 'X' in part numbers indicates power rating (S or L).
2. V
CC
= 3.3V, T
A
= +25°C, and are not production tested. I
CCDC
= 70mA (Typ.).
3. At f = f
MAX
, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/t
RC
and using "AC Test Conditions" of input levels
of GND to 3V.
4. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby.
5. Port "A" may be either left or right port. Port "B" is opposite from port "A".
Data Retention Characteristics
(L Version Only)
Symbol
V
DR
I
CCDR
t
CDR
(3)
Parameter
V
CC
for Data Retention
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery Time
V
CC
= 2
V,
CE
> V
CC
- 0.2V
V
IN
> V
CC
- 0.2V or V
IN
< 0.2V
COM'L.
IND.
Test Condition
Min.
2.0
___
Typ.
___
(1)
Max.
0
500
1000
___
Unit
V
µA
µA
V
V
3026 tbl 07
100
100
___
___
0
t
R
(3)
t
RC
(2)
___
___
NOTES:
1. V
CC
= 2V, T
A
= +25°C, and is not production tested.
2. t
RC
= Read Cycle Time.
3. This parameter is guaranteed by device characterization but not production tested.
4
6.42
IDT71V321/71V421S/L
High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
AC Test Conditions
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
5ns
1.5V
1.5V
Figures 1 and 2
3026 tbl 08
Data Retention Waveform
DATA RETENTION MODE
V
DR
≥
2.0V
V
CC
3.0V
t
CDR
3.0V
t
R
CE
V
IH
V
DR
V
IH
3026 drw 04
,
3.3V
590Ω
DATA
OUT
BUSY
INT
435Ω
DATA
OUT
30pF
435Ω
3.3V
590Ω
5pF
3026 drw 05
Figure 1. AC Output Test Load
Figure 2. Output Test Load
(for t
HZ
, t
LZ
, t
WZ
, and t
OW
)
* Including scope and jig.
AC Electrical Characteristics Over the
Operating Temperature Supply Voltage Range
(2)
71V321X25
71V421X25
Com'l & Ind
Symbol
READ CYCLE
t
RC
t
AA
t
ACE
t
AOE
t
OH
t
LZ
t
HZ
t
PU
t
PD
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Output Hold from Address Change
Output Low-Z Time
(1,2)
Output High-Z Time
(1,2)
Chip Enable to Power Up Time
(2)
Chip Disable to Power Down Time
(2)
25
____
____
____
71V321X35
71V421X35
Com'l & Ind
Min.
Max.
71V321X55
71V421X55
Min.
Max.
Unit
Parameter
Min.
Max.
35
____
____
____
55
____
____
____
ns
ns
ns
ns
ns
ns
ns
ns
ns
3026 tbl 09
25
25
12
____
35
35
20
____
55
55
25
____
____
____
____
3
0
____
3
0
____
3
0
____
____
____
____
12
____
15
____
30
____
0
____
0
____
0
____
50
50
50
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. 'X' in part numbers indicates power rating (S or L).
5
6.42
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
