DATA SHEET
FemtoClock® NG Universal Frequency
Translator
Features
•
•
•
IDT8T49N222I
General Description
The IDT8T49N222I is a highly flexible FemtoClock® NG general
purpose, low phase noise Frequency Translator / Synthesizer with
alarm and monitoring functions suitable for networking and
communications applications. It is able to generate any output
frequency in the 7.29MHz to 833.33MHz range and most output
frequencies in the 925MHz to 1200MHz range (see Table 3A for
details). A wide range of input reference clocks and a range of
low-cost fundamental mode crystal frequencies may be used as the
source for the output frequency.
The IDT8T49N222I has three operating modes to support a very
broad spectrum of applications:
1) Frequency Synthesizer
Fourth generation FemtoClock® NG technology
Universal Frequency Translator
•
Zero ppm frequency translation
Two outputs, individually programmable as LVPECL or LVDS
•
Outputs may be individually set to use 2.5V or 3.3V output
levels
•
Individually programmable output frequencies: 7.29MHz up to
1200MHz
Two differential inputs support the following input types:
LVPECL, LVDS, LVHSTL, HCSL
•
Input frequency range: 8kHz to 710MHz
•
Hitless switching between inputs
Crystal input frequency range: 16MHz to 40MHz
•
Holdover support in the event both inputs fail
One factory-set register configuration for power-up default state
•
Configurations customized via One-Time Programmable ROM
•
Settings may be overwritten after power-up via I
2
C
•
I
2
C Serial interface for register programming
RMS phase jitter at 156.25MHz, using a 40MHz crystal
(12kHz - 20MHz): 507fs (typical), Low Bandwidth Mode (FracN)
Supports ITU-T G.8262 Synchronous Ethernet equipment slave
clocks (EEC option 1 and 2)
Output supply voltage modes:
V
CC
/V
CCA
/V
CCOx
3.3V/3.3V/3.3V
3.3V/3.3V/2.5V (LVPECL only)
2.5V/2.5V/2.5V
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
•
•
•
Synthesizes output frequencies from a 16MHz - 40MHz
fundamental mode crystal.
Fractional feedback division is used, so there are no
requirements for any specific crystal frequency to produce the
desired output frequency with a high degree of accuracy.
Applications: PCI Express, Computing, General Purpose
Translates any input clock in the 16MHz - 710MHz frequency
range into any supported output frequency.
This mode has a high PLL loop bandwidth in order to track input
reference changes, such as Spread-Spectrum Clock
modulation, so it will not attenuate much jitter on the input
reference.
Applications: Networking & Communications.
Translates any input clock in the 8kHz –710MHz frequency
range into any supported output frequency.
This mode supports PLL loop bandwidths in the 10Hz - 580Hz
range and makes use of an external crystal to provide
significant jitter attenuation.
•
•
2) High-Bandwidth Frequency Translator
•
•
•
•
•
•
3) Low-Bandwidth Frequency Translator
•
•
•
•
•
This device provides a factory-programmed default power-up
configuration burned into One-Time Programmable (OTP) memory.
The configuration is specified by the customer and is programmed by
IDT during the final test phase from an on-hand stock of blank
devices.
To implement other configurations, these power-up default settings
can be overwritten after power-up using the I
2
C interface and the
device can be completely reconfigured. However, these settings
would have to be written every time the device powers-up.
Pin Assignment
Q0
nQ0
V
EE
OE0
LOCK_IND
V
EE
V
CCO0
nQ1
V
CCO1
V
EE
nc
V
CC
S_AO
S_A1
Reserved
nc
SCLK
SDATA
V
CC
PLL_BYPASS
nc
CLK_ACTIVE
V
EE
LF0
LF1
V
EE
V
EE
nc
V
CCA
HOLDOVER
CLK0BAD
CLK1BAD
XTALBAD
36 35 34 33 32 31 30
29 28 27 26 25
37
24
38
23
39
22
IDT8T49N222I
40
21
48 Lead VFQFN
20
41
7.0mm x 7.0mm x 0.925mm,
42
19
package body
43
18
NL Package
44
17
Top View
45
16
46
15
47
14
48
13
1 2
3
4 5 6 7
8 9
10 11 12
XTAL_OUT
V
CC
CLK_SEL
CLK0
nCLK0
V
CC
nc
V
EE
V
EE
XTAL_IN
CLK1
nCLK1
IDT8T49N222BNLGI REVISION A MAY 13, 2013
1
©2013 Integrated Device Technology, Inc.
OE1
V
EE
Q1
IDT8T49N222I Data Sheet
FemtoClock® NG Universal Frequency Translator
Block Diagram
PLL_BYPASS
XTAL_IN
OSC
XTAL_OUT
x2
PD/LF
FemtoClock® NG
VCO
1
Output Divider
÷N0[7:0]
0
1
Q0
nQ0
OE0
0
Feedback Divider
÷M_INT
[7:0]
÷M_FRAC
[17:0]
÷N1[7:0]
0
1
Q1
nQ1
OE1
LF1
ADC
CLK_SEL
CLK0
nCLK0
CLK1
nCLK1
POR
OTP
÷4
0
1
R
3
÷M1[16:0]
PD/CP
÷P[16:0]
LF0
R
S
C
3
C
P
Control Logic
Global Registers
Register Set
Status Indicators
C
S
CLK_ACTIVE
LOCK_IND
XTALBAD
CLK0BAD
CLK1BAD
HOLDOVER
SCLK, S_A0, S_A1
SDATA
IDT8T49N222BNLGI REVISION A MAY 13, 2013
2
©2013 Integrated Device Technology, Inc.
IDT8T49N222I Data Sheet
FemtoClock® NG Universal Frequency Translator
Pin Descriptions and Pin Characteristic Tables
Table 1. Pin Descriptions
Number
1
2
3, 7, 15, 22
4
5
6
8, 13, 18,
23, 43
9, 10, 24,
28, 30, 33,
38, 41, 42
11
12
Name
XTAL_IN
XTAL_OUT
V
CC
CLK_SEL
CLK0
nCLK0
nc
Input
Power
Input
Input
Input
Unused
Pulldown
Pulldown
Pullup/
Pulldown
Type
Description
Crystal Oscillator interface designed for 12pF parallel resonant crystals.
XTAL_IN (pin 1) is the input and XTAL_OUT (pin 2) is the output.
Core supply pins. All must be either 3.3V or 2.5V.
Input clock select. Selects the active differential clock input.
0 = CLK0, nCLK0 (default)
1 = CLK1, nCLK1
Non-inverting differential clock input.
Inverting differential clock input. V
CC
/2 default when left floating (set by the
internal pullup and pulldown resistors).
No connect. These pins are to be left unconnected.
V
EE
CLK1
nCLK1
Power
Input
Input
Pulldown
Pullup/
Pulldown
Pulldown
Pullup
Pullup
Negative supply pins.
Non-inverting differential clock input.
Inverting differential clock input. V
CC
/2 default when left floating (set by the
internal pullup and pulldown resistors).
Bypasses the VCXO PLL.
0 = PLL Mode (default)
1 = PLL Bypassed
I
2
C Data Input/Output. Open drain.
I
2
C Clock Input. LVCMOS/LVTTL Interface Levels.
Must be left unconnected.
Pulldown
Pulldown
I
2
C Address Bit 1. LVCMOS/LVTTL Interface Levels.
I
2
C Address Bit 0. LVCMOS/LVTTL Interface Levels.
Output supply pins for Q1, nQ1 outputs. Either 2.5V or 3.3V.
Differential output. Output type is programmable to LVDS or LVPECL interface
levels.
Pullup
Active High Output Enable for Q1, nQ1.
0 = Output pins high-impedance
1 = Output switching (default)
Lock Indicator - indicates that the PLL is in a locked condition. LVCMOS/LVTTL
interface levels.
Pullup
Active High Output Enable for Q0, nQ0.
0 = Output pins high-impedance
1 = Output switching (default)
Differential output. Output type is programmable to LVDS or LVPECL interface
levels.
Output supply pins for Q0, nQ0 outputs. Either 2.5V or 3.3V.
Indicates which of the two differential clock inputs is currently selected.
0 = CLK0, nCLK0 differential input pair
1 = CLK1, nCLK1 differential input pair
Loop filter connection node pins. LF0 is the output. LF1 is the input.
14
16
17
19
20
21
25
26, 27
PLL_BYPASS
SDATA
SCLK
Reserved
S_A1
S_A0
V
CCO1
nQ1, Q1
Input
I/O
Input
Unused
Input
Input
Power
Output
29
OE1
Input
31
LOCK_IND
Output
32
OE0
Input
34, 35
36
37
39, 40
nQ0, Q0
V
CCO0
CLK_ACTIVE
LF0, LF1
Output
Power
Output
Input
IDT8T49N222BNLGI REVISION A MAY 13, 2013
3
©2013 Integrated Device Technology, Inc.
IDT8T49N222I Data Sheet
FemtoClock® NG Universal Frequency Translator
Table 1. Pin Descriptions
Number
Name
Type
Description
Continued on next page.
44
V
CCA
Power
Analog supply voltage.
Alarm output reflecting if the device is in a holdover state. LVCMOS/LVTTL
interface levels.
0 = Device is locked to a valid input reference
1 = Device is not locked to a valid input reference
Alarm output reflecting the state of CLK0. LVCMOS/LVTTL interface levels.
0 = Input Clock 0 is switching within specifications
1 = Input Clock 0 is out of specification
Alarm output reflecting the state of CLK1. LVCMOS/LVTTL interface levels.
0 = Input Clock 1 is switching within specifications
1 = Input Clock 1 is out of specification
Alarm output reflecting the state of XTAL. LVCMOS/LVTTL interface levels.
0 = crystal is switching within specifications
1 = crystal is out of specification
45
HOLDOVER
Output
46
CLK0BAD
Output
47
CLK1BAD
Output
48
XTALBAD
Output
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
HOLDOVER,
CLK_ACTIVE,
CLK0BAD, CLK1BAD,
XTALBAD, LOCK_IND
HOLDOVER,
CLK_ACTIVE,
CLK0BAD, CLK1BAD,
XTALBAD, LOCK_IND
Test Conditions
Minimum
Typical
3.5
51
51
Maximum
Units
pF
k
k
V
CC
= 3.465V
25
R
OUT
Output
Impedance
V
CC
= 2.625V
25
IDT8T49N222BNLGI REVISION A MAY 13, 2013
4
©2013 Integrated Device Technology, Inc.
IDT8T49N222I Data Sheet
FemtoClock® NG Universal Frequency Translator
Functional Description
The IDT8T49N222I is designed to provide two output frequencies
almost anywhere within its supported output frequency range
(7.29MHz to 1200MHz) from any input source in the supported input
frequency range (8kHz to 710MHz). It is capable of synthesizing
frequencies from a crystal or crystal oscillator source. The output
frequency is generated regardless of the relationship to the input
frequency. The output frequency will be exactly the required
frequency in most cases. In most others, it will only differ from the
desired frequency by a few ppb. IDT configuration software will
indicate the frequency error, if any. The IDT8T49N222I can translate
the desired output frequency from one of two input clocks. Again, no
relationship is required between the input and output frequencies in
order to translate to the output clock rate. In this frequency translation
mode, a low-bandwidth, jitter attenuation option is available that
makes use of an external fixed-frequency crystal or crystal oscillator
to translate from a noisy input source. If the input clock is known to
be fairly clean or if some modulation on the input needs to be tracked,
then the high-bandwidth frequency translation mode can be used,
without the need for the external crystal.
The input clock references and crystal input are monitored
continuously and appropriate alarms are raised both as register bits
and hard-wired pins in the event of any out-of-specification conditions
arising. Clock switching is supported in manual, revertive &
non-revertive modes.
The IDT8T49N222I has one factory-programmed configuration that
sets the default operating state after reset. These defaults may be
over-written by I
2
C register access at any time, but those over-written
settings will be lost on power-down. Please contact IDT if a specific
set of power-up default settings is desired. Users that have a custom
configuration programmed may not require I
2
C access.
Please make use of IDT-provided configuration tools to determine the
best operating settings for the desired configurations of the device.
Please refer to the Universal Frequency Translator Family
Programming Guide if further details are required.
Operating Modes
The IDT8T49N222I has three operating modes which are set by the
MODE_SEL[1:0] bits. There are two frequency translator modes -
low bandwidth and high bandwidth and a frequency synthesizer
mode.
Please make use of IDT-provided configuration applications to
determine the best operating settings for the desired configurations
of the device.
Output Dividers & Supported Output Frequencies
The internal VCO is capable of operating in a range from 1.850GHz
up to 2.5GHz. The output divider stages N0[7:0] and N1[7:0] are
limited to selection of integers from 2 to 254. Please refer to Table 3A
for the recommended values of N applicable to the desired output
frequency.
Table 3A. Output Divider Settings & Frequency Ranges*
Register
Setting
Nn[7:0]
0000000x
00000010
00000011
00000100
00000101
00000110
00000111
00001000
00001001
00001010
11111110
2
3
4
5
6
7
8
9
10
...
254
7.29
9.84
Frequency
Divider
Nn
Minimum
f
OUT
(MHz)
Not Supported
925.00
616.67
462.50
370.00
308.33
264.29
231.25
205.56
185.00
1200.00
833.33
625.00
500.00
416.67
357.14
312.50
277.78
250.00
Maximum
f
OUT
(MHz)
*NOTE: Frequency ranges for other N output dividers are possible.
Contact IDT Factory for special cases.
In addition to the above output divider settings, it is possible for either
or both of the outputs to present a copy of the currently active input
reference frequency by asserting the appropriate BYPn register bit.
IDT8T49N222BNLGI REVISION A MAY 13, 2013
5
©2013 Integrated Device Technology, Inc.
PCB设计
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
