LVCMOS Clock Generator
870931I-01
Data Sheet
General Description
The 870931I-01 is an LVCMOS clock generator that uses an internal
phase lock loop (PLL) for frequency multiplication and to lock the
low-skew outputs to the reference clock. The device offers six
outputs. The PLL loop filter is completely internal and does not
require external components. Several combinations of the PLL
feedback and a divide-by-2 (controlled by FREQ_SEL) allow
applications to optimize frequency generation over a wide range of
input reference frequencies. The PLL can also be disabled by the
PLL_EN control signal to allow for low frequency or DC testing. The
870931I-01 device is a member of the family of high performance
clock solutions from IDT.
Features
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Single-ended input reference clock
Six single-ended clock outputs
Internal PLL does not require external loop filter components
5V tolerant inputs
Maximum output frequency: 80MHz, (Q0:Q4 outputs)
Maximum output frequency: 40MHz, (Q/2 output)
LVCMOS interface levels for all inputs and outputs
PLL disable feature for low-frequency testing
Output drive capability: ±24mA
Output skew: 300ps (maximum), Q0:Q4 and Q/2
Full 3.3V supply voltage
Available in lead-free packages
-40°C to 85°C ambient operating temperature
Fully pin and function compatible with the IDTQS5LV931
(including 50, 66 and 80MHz options)
Pin Assignment
GND
OE/nRST
FEEDBACK
AV
DD
V
DD
AGND
SYNC
FREQ_SEL
GND
Q0
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Q4
Q/2
GND
Q3
V
DD
Q2
GND
PLL_EN
GND
Q1
870931I-01
20-Lead QSOP, 150Mil
3.9mm x 8.65mm x 1.5mm package body
R Package
Top View
Block Diagram
0
1
0
÷2
Q0
Q1
Q2
Q3
SYNC
1
f
REF
PLL
f
VCO
20MHz - 160MHz
÷2
FEEDBACK
÷4
Q4
Q/2
PLL_EN
FREQ_SEL
©2016 Integrated Device Technology, Inc
1
Revision B April 25, 2016
870931I-01 Data Sheet
Table 1. Pin Descriptions
Number
1, 9, 12, 14, 18
2
3
4
5, 16
6
7
8
10, 11,
15, 17, 20
13
19
Name
GND
OE/nRST
FEEDBACK
AV
DD
V
DD
AGND
SYNC
FREQ_SEL
Q0, Q1,
Q2, Q3, Q4
PLL_EN
Q/2
Type
Power
Input
Input
Power
Power
Power
Input
Input
Description
Power supply ground.
Output enable and asynchronous reset. Resets all outputs. Logic LOW, the outputs are in
high-impedance state. Logic HIGH enables all outputs. LVCMOS/LVTTL interface levels.
PLL feedback input which is connected to one of the clock outputs to close the PLL
feedback loop. LVCMOS/LVTTL interface levels.
Positive power supply for the PLL.
Positive power supply pins.
Power supply ground for the PLL.
Single-ended reference clock input. LVCMOS/LVTTL interface levels.
Frequency select. Logic LOW level inserts a divide-by-2 into the PLL output and feedback
path. Logic HIGH inserts a divide-by-1 into the PLL output and feedback path.
LVCMOS/LVTTL interface levels.
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
PLL enable. Enable and disables the PLL. Logic HIGH enables the PLL. Logic LOW
disables the PLL and the input reference signal is routed to the output dividers (PLL
bypass). LVCMOS/LVTTL interface levels.
Single-ended clock output. LVCMOS/LVTTL interface levels.
Output
Input
Output
Table 2. Pin Characteristics
Symbol
C
IN
C
PD
R
OUT
Parameter
Input Capacitance
Power Dissipation Capacitance
Output Impedance
V
DD
= AV
DD
= 3.6V
Test Conditions
Minimum
Typical
4
330
11
Maximum
Units
pF
pF
©2016 Integrated Device Technology, Inc
2
Revision B April 25, 2016
870931I-01 Data Sheet
Device Configuration
The 870931I-01 requires a connection to one of the clock outputs to the FEEDBACK input to close the PLL feedback path. The selection of the
output (output divider) for PLL feedback will impact the device configuration and input to output frequency ratio and frequency ranges. See
Table
3D for details.
Function Tables
Table 3A. OE/nRST Mode Configuration Table
Input
OE/nRST
0
1
Operation
Device is reset and the outputs Q0:Q4 and Q/2 are in high-impedance state. This control is asynchronous.
Outputs are enabled.
Table 3B. FREQ_SEL Mode Configuration Table
Input
FREQ_SEL
0
1
Operation
The VCO output is frequency-divided by 2. This setting allows for a lower input frequency range.
See also table 3D for available frequency ranges.
The VCO output is frequency-divided by 1. This setting allows for a higher input frequency range.
See also table 3D for available frequency ranges.
Table 3C. PLL_EN Mode Configuration Table
Input
PLL_EN
0
1
Operation
The PLL is bypassed. The input reference clock is routed to the output dividers for low-frequency board test purpose.
The PLL-related AC specifications do not apply in PLL bypass mode.
The PLL is enabled and locks to the input reference signal.
Table 3D. Frequency Configuration Table
Input Frequency Range
(MHz)
FREQ_SEL
0
1
0
Q/2
1
5 - 40
10 - 80 (2x)
5 - 40 (1x)
SYNC
5 - 40
10 - 80
2.5 - 20
Output Frequency Range (MHz) and
Output-to-Input Frequency Multiplication Factor
Q[0:4]
5 - 40 (1x)
10 - 80 (1x)
5 - 40 (2x)
Q/2
2.5 - 20 (0.5x)
5 - 40 (0.5x)
2.5 - 20 (1x)
Outputs Used for
PLL Feedback
Q0, Q1, Q2,
Q3 or Q4
©2016 Integrated Device Technology, Inc
3
Revision B April 25, 2016
870931I-01 Data Sheet
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
DD
+ 0.5V
-0.5V to V
DD
+ 0.5V
72.3°C/W (0 lfpm)
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, V
DD
= AV
DD
= 3.3V ± 0.3V, T
A
= -40°C to 85°C
Symbol
V
DD,
AV
DD
I
DDQ
Parameter
Positive Supply Voltage
Quiescent Power Supply
Current
V
DD
= AV
DD
= Max., OE/nRST = 0,
SYNC =0, All Outputs Open
Test Conditions
Minimum
3.0
Typical
3.3
Maximum
3.6
5
Units
V
mA
Table 4B. LVCMOS/LVTTL DC Characteristics, V
DD
= AV
DD
= 3.3V ± 0.3V, T
A
= -40°C to 85°C
Symbol
V
IH
V
IL
I
IH
Parameter
Input High Voltage
Input Low Voltage
Input High Current
SYNC, OE/nRST,
FEEDBACK, PLL_EN,
FREQ_SEL
SYNC, OE/nRST,
FEEDBACK, PLL_EN,
FREQ_SEL
Q0:Q4, Q/2
Q0:Q4, Q/2
Q0:Q4, Q/2
V
DD
= V
IN
= 3.3V
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
DD
+ 0.3
0.8
5
Units
V
V
µA
I
IL
V
OH
V
OL
I
OZ
Input Low Current
Output High Voltage:
Output Low Voltage
Output Leakage
Current
V
DD
= 3.3V, V
IN
= 0V
I
OH
= -24 mA
I
OL
= 24 mA
OE/nRST = 0,
V
OUT
= 0V or V
DD
,
V
DD
= 3.6V
-5
2.6
0.5
±5
µA
V
V
µA
©2016 Integrated Device Technology, Inc
4
Revision B April 25, 2016
870931I-01 Data Sheet
Table 5. AC Electrical Characteristics, V
DD
= AV
DD
= 3.3V ± 0.3V, T
A
= -40°C to 85°C
Symbol
Parameter
Test Conditions
Feedback of Q0:Q4, FREQ_SEL = 0
f
REF
SYNC Input Reference
Frequency
Feedback of Q0:Q4, FREQ_SEL = 1
Feedback of Q/2, FREQ_SEL = 0
Feedback of Q/2, FREQ_SEL = 1
f
OUT
idc
t
R
/ t
F
tsk(o)
t
PW
tjit(cc)
Output Frequency
Input Duty Cycle
Input Rise/ Fall Time
Output Skew; NOTE 1, 2, 3
Output Skew; NOTE 1, 2, 3
Output
Pulse Width
Q0:Q4
Q/2
Q0-Q4
Q/2
SYNC
SYNC
Rising edges of Q0:Q4 and Q/2
Falling edges of Q0:Q4
80MHz
40MHz
Feedback = Q
Feedback = Q/2
t
PERIOD
/2 - 0.5
t
PERIOD
/2 - 0.4
25
Minimum
5
10
2.5
5
Typical
Maximum
40
80
20
40
80
40
75
3
300
300
t
PERIOD
/2 + 0.5
t
PERIOD
/2 + 0.4
320
530
Units
MHz
MHz
MHz
MHz
MHz
MHz
%
ns
ps
ps
ns
ns
ps
ps
Cycle-to-Cycle Jitter
Static Phase
Offset, (SYNC to
Q0:Q4
FEEDBACK
delay); NOTE 2, 4
Output Enable
Time; NOTE 5
Output Disable
Time; NOTE 5
Output
Rise/ Fall Time
PLL Lock Time
OE/nRST
OE/nRST
Q0:Q4,
Q/2
t
80MHz
-500
500
ps
t
PZL
t
PHZ,
t
PLZ
t
R
/ t
F
t
LOCK
Low-to-High
High-to-Low
0.8V – 2.0V
0.2
14
14
2
10
ns
ns
ns
ms
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V
DD
/2.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Measured between coincident rising output edges of Q0:Q4 and Q/2.
NOTE 4: Defined as the time difference between the input reference clock and the average feedback input signal when the PLL is locked and
the input reference frequency is stable.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
©2016 Integrated Device Technology, Inc
5
Revision B April 25, 2016
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