2.5V Differential LVDS Clock Divider
and Fanout Buffer
874208I
DATA SHEET
General Description
The 874208I is a high-performance differential LVDS clock divider
and fanout buffer. The device is designed for the frequency division
and signal fanout of high-frequency, low phase-noise clocks. The
874208I is characterized to operate from a 2.5V power supply.
Guaranteed output-to-output and part-to-part skew characteristics
make the 874208I ideal for those clock distribution applications
demanding well-defined performance and repeatability. The
integrated input termination resistors make interfacing to the
reference source easy and reduce passive component count. Each
output can be individually enabled or disabled in the high-impedance
state controlled by a I
2
C register. On power-up, all outputs are
enabled.
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
One differential input reference clock
Differential pair can accept the following differential input
levels: LVDS, LVPECL, CML
Integrated input termination resistors
Eight LVDS outputs
Selectable clock frequency division of ÷1, ÷2, ÷4 and ÷8
Maximum input clock frequency: 500MHz
LVCMOS interface levels for the control inputs
Internal regulator for improved noise immunity
Individual output enable/disabled by I
2
C interface
Output skew: 28ps
Additive Phase Jitter, RMS: 0.168ps (typical), 125MHz
Low additive phase jitter
Full 2.5V supply voltage
Available in Lead-free (RoHS 6) package
-40°C to 85°C ambient operating temperature
Block Diagram
Q0
nQ0
Q1
nQ1
f
REF
Pin Assignment
SDA
FSEL1
ADR0
SCL
V
DD
nIN
VT
IN
32 31 30 29 28 27 26 25
ADR1
GND
Q0
nQ0
Q1
1
2
3
4
5
6
7
8
9
Q2
24
23
22
21
20
19
18
17
10 11 12 13 14 15 16
nQ4
nQ2
nQ3
nQ5
Q3
Q4
Q5
FSEL0
GND
nQ7
Q7
nQ6
Q6
GND
V
DDO
IN
nIN
50
50
÷1, ÷2,
÷4, ÷8
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
V
T
FSEL[1:0]
Pulldown (2)
nQ1
GND
V
DDO
SDA
SCL
ADR[1:0]
Pullup
Pullup
Pulldown (2)
2
I
2
C
ICS874208I
32 Lead VFQFN
5mm x 5mm x 0.925mm package body
K Package
Top View
8
Q6
nQ6
Q7
nQ7
REVISION A 9/18/14
1
©2014 Integrated Device Technology, Inc.
874208I Data Sheet
LVDS CLOCK DIVIDER AND FANOUT BUFFER
Table 1. Pin Descriptions
Number
1,
32
2, 7, 18, 23
3, 4
5, 6
8, 17
9, 10
11, 12
13, 14
15, 16
19, 20
21, 22
24, 25
26
27
28
29
30
31
Name
ADR1,
ADR0
GND
Q0, nQ0
Q1, nQ1
V
DDO
Q2, nQ2
Q3, nQ3
Q4, nQ4
Q5, nQ5
Q6, nQ6
Q7, nQ7
FSEL0,
FSEL1
IN
V
T
nIN
V
DD
SDA
SCL
Input
Power
Output
Output
Power
Output
Output
Output
Output
Output
Output
Input
Input
Termination
input
Input
Power
I/O
Input
Pullup
Pullup
Pulldown
Type
Pulldown
Description
I
2
C Address inputs. LVCMOS/LVTTL compatible interface levels.
Power supply ground.
Differential output pair 0. LVDS interface levels.
Differential output pair 1. LVDS interface levels.
Output power supply pins.
Differential output pair 2. LVDS interface levels.
Differential output pair 3. LVDS interface levels.
Differential output pair 4. LVDS interface levels.
Differential output pair 5. LVDS interface levels.
Differential output pair 6. LVDS interface levels.
Differential output pair 7. LVDS interface levels.
Frequency divider select controls. See Table 3A for function.
LVCMOS/LVTTL interface levels.
Non-inverting differential clock input.
Input for termination. Both IN and nIN inputs are internally terminated 50 to
this pin. See input termination information in the applications section.
Inverting differential clock input.
Power supply pins.
I
2
C Data Input/Output. Input: LVCMOS/LVTTL interface levels.
Output: open drain.
I
2
C clock input. LVCMOS/LVTTL compatible interface levels.
NOTE:
Pulldown
and
Pullup
refers to an internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLDOWN
R
PULLUP
Parameter
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
k
k
REVISION A 9/18/14
2
©2014 Integrated Device Technology, Inc.
874208I Data Sheet
LVDS CLOCK DIVIDER AND FANOUT BUFFER
Function Tables
Input Frequency Divider Operation
The FSEL1 and FSEL0 controls configure the input frequency
divider. In the default state (FSEL[1:0] are set to logic 0:0 or left open)
the output frequency is equal to the input frequency (divide-by-1).
The other FSEL[1:0] settings configure the input divider to ÷2, ÷4 or
÷8, respectively.
Table 3A. FSEL[1:0] Input Selection Function Table
Input
FSEL1
0 (default)
0
1
1
FSEL0
0 (default)
1
0
1
Operation
f
Q[7:0]
= f
REF
÷ 1
f
Q[7:0]
= f
REF
÷ 2
f
Q[7:0]
= f
REF
÷ 4
f
Q[7:0]
= f
REF
÷ 8
to make up the complete I
2
C transactions as shown in Figure 2 and
Figure 3. Figure 2 is a write transaction while Figure 3 is read
transaction. The 7-bit I
2
C slave address of the 874208I is a
combination of a 4-bit fixed addresses and two variable bits which are
set by the hardware pins ADR[1:0] (binary 11010, ADR1, ADR0). Bit
0 of slave address is used by the bus controller to select either the
read or write mode. The hardware pins ADR1 and ADR0 should be
individually set by the user to avoid address conflicts of multiple
874208I devices on the same bus.
Table 3D. I
2
C Slave Address
7
1
6
1
5
0
4
1
3
0
2
ADR1
1
ADR0
0
R/W
NOTE: FSEL1, FSEL0 are asynchronous controls
Output Enable Operation
The output enable/disable state of each individual differential output
Qx can be set by the content of the I
2
C register (see Table 3C). A
logic zero to an I
2
C bit in register 0 enables the corresponding
differential output, while a logic one disables the differential output
(see Table 3B). After each power cycle, the device resets all I
2
C bits
(D[7:0]) to its default state (logic 0) and all Qx outputs are enabled.
After the first valid I
2
C write, the output enable state is controlled by
the I
2
C register. Setting and changing the output enable state through
the I
2
C interface is asynchronous to the input reference clock.
Table 3B. Individual Output Enable Control
Bit
D[7:0]
0 (default)
1
Operation
Output Qx, nQx is enabled.
Output Qx, nQx is high-impedance.
Figure 1: Standard I
2
C Transaction
START (ST)
– defined as high-to-low transition on SDA while holding
SCL HIGH.
DATA
– between START and STOP cycles, SDA is synchronous with
SCL. Data may change only when SCL is LOW and must be stable
when SCL is HIGH.
ACKNOWLEDGE (AK)
– SDA is driven LOW before the SCL rising
edge and held LOW until the SCL falling edge.
STOP (SP)
– defined as low-to-high transition on SDA while holding
SCL HIGH
S
D1
Q1
0
D0
Q0
0
DevAdd
W A
Data Byte
A P
Table 3C. Individual output enable control
Bit
Output
Default
D7
Q7
0
D6
Q6
0
D5
Q5
0
D4
Q4
0
D3
Q3
0
D2
Q2
0
Figure 2: Write Transaction
S
DevAdd
R A
Data Byte
A P
Figure 3: Read Transaction
S
–
W
–
R
–
A
–
DevAdd
–
RegAdd
–
P
–
Start or Repeated Start
R/~W is set for Write
R/~W is set for Read
Ack
7 bit Device Address
8 bit Register Address, MSB = Q7 and LSB = Q0
Stop
I
2
C I
nterface Protocol
The ICS874208I uses an
slave interface for writing and reading
the device configuration to and from the on-chip configuration
registers. This device uses the standard I
2
C write format for a write
transaction, and a standard I
2
C read format for a read transaction.
Figure 1 defines the I
2
C elements of the standard I
2
C transaction.
These elements consist of a start bit, data bytes, an acknowledge or
Not-Acknowledge bit and the stop bit. These elements are arranged
REVISION A 9/18/14
3
I
2
C
©2014 Integrated Device Technology, Inc.
874208I Data Sheet
LVDS CLOCK DIVIDER AND FANOUT BUFFER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
(LVDS)
Continuos Current
Surge Current
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Maximum Junction Temperature, TJ
MAX
ESD - Human Body Model; NOTE 1
ESD - Charged Device Model; NOTE 1
Rating
4.5V
-0.5V to V
DD
+ 0.5V
10mA
15mA
33.1°C/W (0 mps)
-65C to 150C
125°C
2000V
500V
NOTE 1: According to JEDEC/JESD 22-A114/22-C101. ESD ratings are target specifications.
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, V
DD
= V
DDO
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Power Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
Test Conditions
Minimum
2.375
2.375
Typical
2.5V
2.5V
Maximum
2.625
2.625
15
203
Units
V
V
mA
mA
Table 4B. LVCMOS/LVTTL Input DC Characteristics, V
DD
= V
DDO
= 2.5V, T
A
= -40°C to 85°C
Symbol
V
IH
V
IL
I
IH
Parameter
Input High Voltage
Input Low Voltage
FSEL1, FSEL0, ADR[1:0]
Input High Current
SCK, SDA
FSEL1, FSEL0, ADR[1:0]
I
IL
V
IN
V
CMR
V
DIFF
R
IN
R
IN,
D
IFF
Input Low Current
SCK, SDA
Input Voltage Swing
IN, nIN
V
DD
= V
IN
= 2.625V
V
DD
= V
IN
= 2.625V
V
DD
= 2.625V, V
IN
= 0V
V
DD
= 2.625V, V
IN
= 0V
-5
-150
0.15
1.2
0.3
45
90
50
100
1.2
V
DD
2.4
66
132
Test Conditions
Minimum
1.7
-0.3
Typical
Maximum
V
DD
+ 0.3
0.7
150
5
Units
V
V
µA
µA
µA
µA
V
V
V
Common Mode Input Voltage; NOTE 1
Differential Input
Voltage Swing
Input Resistance
Differential Input
Resistance
IN, nIN
IN, nIN to V
T
IN to nIN, V
T
= open
NOTE 1: Common mode input voltage is defined as V
IH
.
REVISION A 9/18/14
4
©2014 Integrated Device Technology, Inc.
874208I Data Sheet
LVDS CLOCK DIVIDER AND FANOUT BUFFER
Table 4C. LVDS DC Characteristics, V
DD
= V
DDO
= 2.5V, T
A
= -40°C to 85°C
Symbol
V
OD
V
OD
V
OS
V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
1.09
Test Conditions
Minimum
400
Typical
460
15
1.15
2
Maximum
600
94
1.18
14
Units
mV
mV
V
mV
AC Electrical Characteristics
Table 5. AC Electrical Characteristics, V
DD
= V
DDO
= 2.5V, T
A
= -40°C to 85°C
Symbol
f
REF
Parameter
Input Frequency
Test Conditions
IN, nIN
FSEL[1:0] = 00
f
OUT
Output Frequency
FSEL[1:0] = 01
FSEL[1:0] = 10
FSEL[1:0] = 11
f
SCK
I
2
C Clock Frequency
Buffer Additive Phase Jitter,
RMS; refer to Additive Phase
Jitter Section, measured with
FSEL[1:0] = 00
f
REF
= 100MHz,
Integration Range: 1MHz – 20MHz
f
REF
= 125MHz,
Integration Range: 1MHz – 20MHz
f
REF
=156.25,
Integration Range: 1MHz – 20MHz
FSEL[1:0] = 00
t
PD
Propagation Delay; NOTE 1
FSEL[1:0] = 01
FSEL[1:0] = 10
FSEL[1:0] = 11
tsk(o)
tsk(p)
tsk(pp)
Output Skew; NOTE 2, 3
Pulse Skew
Part-to-Part Skew; NOTE 3, 4, 5
Any Frequency
odc
Output Duty Cycle; NOTE 6
at f
REF
= 100MHz
at f
REF
= 125MHz
at f
REF
= 156.25MHz
t
PDZ
t
R
/ t
F
Output Enable and Disable Time;
NOTE 7
Output Rise/ Fall Time
Output enable/disable state from/to
active/inactive
20% to 80%
200
422
48
48
48
50
50
50
50
52
52
52
1
650
1.30
210
2.60
2.90
Minimum
Typical
Maximum
500
500
250
125
62.5
400
Units
MHz
MHz
MHz
MHz
MHz
kHz
ps
ps
ps
ns
ns
ns
ns
ps
ps
ps
%
%
%
%
µs
ps
0.214
0.168
0.124
1.89
2.60
3.33
3.73
0.260
0.208
0.152
2.30
2.80
3.60
4.00
t
JIT
28
27
60
50
600
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross
points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 5: Part-to-part skew specification does not guarantee divider synchronization between devices
NOTE 6: If FSEL[1:0] = 00 (divide-by-one), the output duty cycle will depend on the input duty cycle.
NOTE 7: Measured from SDA rising edge of I
2
C stop command.
REVISION A 9/18/14
5
©2014 Integrated Device Technology, Inc.
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