Table of Contents
Chapter 1. Introduction .......................................................................................................................... 4
Quick Facts ........................................................................................................................................................... 4
Features ................................................................................................................................................................ 8
Chapter 2. Functional Description ...................................................................................................... 10
General Description ............................................................................................................................................ 10
Field Polynomial......................................................................................................................................... 11
Generator Polynomial ................................................................................................................................ 11
Shortened Codes ....................................................................................................................................... 11
Output Latency........................................................................................................................................... 11
Functional Description......................................................................................................................................... 11
Multiplier Array ........................................................................................................................................... 11
Adder Array ................................................................................................................................................ 11
Remainder Array ........................................................................................................................................ 12
Control........................................................................................................................................................ 12
Basis Conversion Modules......................................................................................................................... 12
Signal Descriptions ............................................................................................................................................. 12
Timing Specifications .......................................................................................................................................... 13
Chapter 3. Parameter Settings ............................................................................................................ 17
Reed-Solomon Encoder Configuration GUI ........................................................................................................ 18
Core Configuration ..................................................................................................................................... 18
RS Parameters........................................................................................................................................... 18
Check Symbols .......................................................................................................................................... 19
Block Size Type ......................................................................................................................................... 19
Implementation Parameters ....................................................................................................................... 19
Optional Output Ports................................................................................................................................. 19
Summary............................................................................................................................................................. 20
Chapter 4. IP Core Generation............................................................................................................. 21
Licensing the IP Core.......................................................................................................................................... 21
Getting Started .................................................................................................................................................... 21
IPexpress-Created Files and Top Level Directory Structure............................................................................... 23
Instantiating the Core .......................................................................................................................................... 25
Running Functional Simulation ........................................................................................................................... 25
Synthesizing and Implementing the Core in a Top-Level Design ....................................................................... 25
Hardware Evaluation........................................................................................................................................... 26
Enabling Hardware Evaluation in Diamond:............................................................................................... 26
Enabling Hardware Evaluation in ispLEVER:............................................................................................. 26
Updating/Regenerating the IP Core .................................................................................................................... 26
Regenerating an IP Core in Diamond ........................................................................................................ 26
Regenerating an IP Core in ispLEVER ...................................................................................................... 27
Chapter 5. Support Resources ............................................................................................................ 28
Lattice Technical Support.................................................................................................................................... 28
Online Forums............................................................................................................................................ 28
Telephone Support Hotline ........................................................................................................................ 28
E-mail Support ........................................................................................................................................... 28
Local Support ............................................................................................................................................. 28
Internet ....................................................................................................................................................... 28
References.......................................................................................................................................................... 28
LatticeECP ........................................................................................................................................... /EC28
LatticeECP2M ............................................................................................................................................ 28
© 2010 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
IPUG40_03.6, August 2010
2
Dynamic Block Reed-Solomon Encoder User’s Guide
Lattice Semiconductor
Table of Contents
LatticeECP3 ............................................................................................................................................... 29
LatticeSC/M................................................................................................................................................ 29
LatticeXP.................................................................................................................................................... 29
LatticeXP2.................................................................................................................................................. 29
Related Information............................................................................................................................................. 29
Revision History .................................................................................................................................................. 29
Appendix A. Resource Utilization ....................................................................................................... 30
LatticeECP and LatticeEC FPGAs ...................................................................................................................... 30
Ordering Part Number................................................................................................................................ 30
LatticeECP2 and LatticeECP2S FPGAs ............................................................................................................. 31
Ordering Part Number................................................................................................................................ 31
LatticeECP2M and LatticeECP2MS FPGAs ....................................................................................................... 32
Ordering Part Number................................................................................................................................ 32
LatticeECP3 FPGAs............................................................................................................................................ 32
Ordering Part Number................................................................................................................................ 32
LatticeXP FPGAs ................................................................................................................................................ 33
Ordering Part Number................................................................................................................................ 33
LatticeXP2 FPGAs .............................................................................................................................................. 33
Ordering Part Number................................................................................................................................ 33
LatticeSC and LatticeSCM FPGAs ..................................................................................................................... 34
Ordering Part Number................................................................................................................................ 34
IPUG40_03.6, August 2010
3
Dynamic Block Reed-Solomon Encoder User’s Guide
Chapter 1:
Introduction
Lattice's Dynamic Block Reed-Solomon Encoder IP core can be used for forward error correction in many terres-
trial communication, space communication, data storage, and data retrieval systems. The encoder is compliant
with several industrial standards including the more recent IEEE 802.16-2004. The Reed-Solomon Encoder IP core
provides a customizable solution allowing forward error correction in other non-standard applications as well.
The encoder supports both a fixed, as well as a variable number of total symbols (block) and check symbols. In the
variable configurations, either the block size or both the block size and check symbols can be dynamically varied
through ports. The core allows dynamic output check symbols puncturing in the fixed check symbols configura-
tions.
This user's guide describes the functionality and implementation of the Reed-Solomon Encoder. Lattice also offers
a Reed-Solomon Decoder core that can serve as a complementary pair for decoding. For more information on Lat-
tice products, refer to the Lattice web site at
www.latticesemi.com.
Quick Facts
Table 1-1
through
Table 1-9
give quick facts about the Dynamic Block Reed-Solomon Encoder IP core for Lat-
ticeEC™, LatticeECP™, LatticeECP2™, LattceECP2M™, LattticeSC™, LatticeSCM™, LatticeXP™,
LatticeXP2™, and LatticeECP3™ devices.
Table 1-1. Dynamic Block Reed-Solomon Encoder IP core for LatticeEC Devices Quick Facts
Dynamic Block Reed-Solomon Encoder IP Configuration
IEEE
802.16-
2004 SCa
IEEE
802.16-
2004 SC
OC-192
Core
Requirements
FPGA Families Supported
Minimal Device Needed
Targeted Device
Resource
Utilization
LUTs
sysMEM EBRs
Registers
Lattice Implementation
Design Tool
Support
Synthesis
Simulation
300
0
300
LFEC1E
CCSDS
DVB
ATSC
Lattice EC
LFEC1E
LFEC1E
LFEC1E
LFEC1E
LFEC3E
LFEC20E-5F672C
500
0
400
300
0
300
400
0
300
400
0
300
2700
0
600
Diamond
®
1.0 or ispLEVER
®
8.1
Synopsys
®
Synplify
™
Pro for Lattice D-2009.12L-1
Aldec
®
Active-HDL
™
8.2 Lattice Edition
Mentor Graphics
®
ModelSim
™
SE 6.3F
IPUG40_03.6, August 2010
4
Dynamic Block Reed-Solomon Encoder User’s Guide
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
