ispLever
CORE
TM
Reed-Solomon Encoder
User’s Guide
October 2005
ipug05_03.0
Lattice Semiconductor
Reed-Solomon Encoder User’s Guide
Introduction
Lattice’s Reed-Solomon Encoder core provides an ideal solution that meets the needs of today’s Reed-Solomon
applications. The Reed-Solomon Encoder core provides a customizable solution allowing forward error correction
in many design applications. This core allows designers to focus on the application rather than the Reed-Solomon
Encoder, resulting in faster time to market.
Reed-Solomon codes are widely used in various applications for forward error correction and detection. Lattice’s
Reed-Solomon Encoder core is a fully synchronous core developed in conjunction with Lattice’s Reed-Solomon
Decoder core to provide a complimentary pair. For more information on Lattice products, refer to the Lattice web
site at www.latticesemi.com.
This user’s guide illustrates the functionality and implementation of the Reed-Solomon Encoder to provide encod-
ing on any data transmission. It also describes a method for achieving the maximum level of performance.
The Reed-Solomon Encoder Core
This section describes the functionality of the Reed-Solomon Encoder core. It includes information on how to cus-
tomize the Reed-Solomon Encoder core as well as the details necessary to design an application that will interface
with the Reed-Solomon Encoder core. Figure 1 illustrates the functional modules and internal bus structure used in
the Reed-Solomon Encoder core.
Figure 1. Reed-Solomon Encoder Core Block Diagram
Multiplier Array
d_in
Control Bus
Adder Array
Remainder Array
d_out
rstn
enable
byp
start
clk
Control
status
dvalid
rdy
Multiplier Array
The Multiplier Array does the Galois field multiplication between the generator coefficients and the addition of input
data and feedback (modulo 2). This multiplication is an optimized multiplication between the generator coefficients,
which are constants, and the input of the Multiplier Array. This optimization is done when processing the core.
Adder Array
The Adder Array performs addition (modulo 2) on the data from the previous element of the Remainder Array and
the result of the corresponding Galois field multiplication from the Multiplier Array. The outputs from the Adder Array
are latched into the Remainder Array on each clock cycle.
2
Lattice Semiconductor
Remainder Array
Reed-Solomon Encoder User’s Guide
The Remainder Array is a shift register array. It stores the remainder polynomial after the polynomial division. The
remainder polynomial becomes the check symbols once all information symbols have been processed. The
Remainder Array shifts in the data from the Adder Array until no information symbols remain. When all the informa-
tion symbols have been received, the polynomial multiplication stops and the contents of the Remainder Array are
output to
d_out
.
Control Block
The control block generates all control signals and determines the state of the Reed-Solomon Encoder. The inputs
control the state of the encoder. The control signals from the control block are sent through the control bus to deter-
mine when data should be transmitted to the encoder.
Timing Diagrams
The illustrated timing examples utilize a non-continuous RS (7,3) code. The timing remains the same whether the
core is continuous or non-continuous. However, when the core is continuous, the
rdy
and
dvalid
signals are not
used.
Figure 2 illustrates the timing of an RS (7,3) single pipelined encoder during normal operation. The handshake sig-
nals
status
,
rdy
, and
dvalid
display how the encoder communicates with the source and destination devices.
Figure 2. Timing of an RS (7,3) Single Pipelined Encoder
clk
rstn
start
enable
byp
d_in
d_out
status
rdy
dvalid
D6
D5
D4
D6
X3
D5
X2
D4
X1
C3
X0
C2
DN6
C1
DN5
C0
DN4
DN6
3
Lattice Semiconductor
Reed-Solomon Encoder User’s Guide
Figure 3 shows the timing of an RS (7,3) single pipelined encoder with
byp
asserted during the operation of the
encoder. The handshaking signals are identical to normal operation, but the output is shifted due to the extra
bypass data, which does not require check symbols.
Figure 3. Timing of an RS (7,3) Single Pipelined Encoder with
byp
Asserted
clk
rstn
start
enable
byp
d_in
d_out
status
rdy
dvalid
D6
D5
D4
D6
DBP
D5
D4
DBP
C3
C2
DN6
C1
DN5
C0
Figure 4 explains the timing of an RS (7,3) single pipelined encoder with enable de-asserted during the operation
of the encoder. The handshaking signal,
dvalid
, indicates the data on
d_out
is invalid while the encoder main-
tains its state during the time enable is low.
Figure 4. Timing of an RS (7,3) Single Pipelined Encoder with
enable
De-asserted
clk
rstn
start
enable
byp
d_in
d_out
status
rdy
dvalid
D6
D5
D4
D6
XX
D5
X3
D4
X2
D4
X1
C3
X0
C2
DN6
C1
DN5
C0
4
Lattice Semiconductor
Reed-Solomon Encoder User’s Guide
Figure 5 explains the timing of an RS (7,3) single pipelined encoder with start re-asserted during the operation of
the encoder. The handshaking signal,
rdy
, indicates the encoder is ready to receive a new set of data when start is
re-asserted during encoding.
Figure 5. Timing of an RS (7,3) Single Pipelined Encoder with
start
Re-asserted
clk
rstn
start
enable
byp
d_in
d_out
status
rdy
dvalid
D6
D5
D4
D6
X3
D5
D6
D4
D5
C3
D4
D6
X3
D5
X2
D4
X1
C3
Figure 6 illustrates the timing of an RS (7,3) double-pipelined encoder during normal operation. The handshake
signals,
status
,
rdy
, and
dvalid
, display how the encoder communicates with the source and destination
devices.
Figure 6. Timing of an RS (7,3) Double Pipelined Encoder
clk
rstn
start
enable
byp
d_in
d_out
status
rdy
dvalid
D6
D5
D4
X3
D6
X2
D5
X1
D4
X0
C3
DN6
C2
DN5
C1
DN4
C0
5
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