19-3549; Rev 0; 2/05
KIT
ATION
EVALU
BLE
AVAILA
7.5Msps, Ultra-Low-Power
Analog Front-End
General Description
Features
♦
Dual 10-Bit Rx ADC and Dual 10-Bit Tx DAC
♦
Ultra-Low Power
36.3mW at f
CLK
= 5.12Msps, Fast Mode
19.8mW at f
CLK
= 5.12Msps, Slow Mode
Low Standby and Shutdown Current
♦
Integrated TD-SCDMA Filters with >55dB
Stopband Rejection
♦
Excellent Dynamic Performance
SINAD = 54.9dB at f
IN
= 1.87MHz (Rx ADC)
SFDR = 76.5dBc at f
OUT
= 620kHz (Tx DAC)
♦
Excellent Gain/Phase Match
±0.22° Phase, ±0.02dB Gain (Rx ADC) at
f
IN
= 1.87MHz at -0.5dBFS
♦
Three 12-Bit, 1µs Aux-DACs
♦
Single-Supply Operation
♦
Multiplexed Parallel Digital I/O
♦
Serial-Interface Control
♦
Versatile Power-Control Circuits
Shutdown, Standby, Idle, Tx-Rx Disable
♦
Miniature 48-Pin Thin QFN Package
(7mm x 7mm x 0.8mm)
MAX19700
The MAX19700 is an ultra-low-power, mixed-signal ana-
log front-end (AFE) designed for TD-SCDMA handsets
and data cards. Optimized for high dynamic perfor-
mance at ultra-low power, the MAX19700 integrates a
dual 10-bit, 7.5Msps receive (Rx) ADC, dual 10-bit,
7.5Msps transmit (Tx) DAC with TD-SCDMA baseband
filters, and three fast-settling 12-bit aux-DAC channels
for ancillary RF front-end control. The typical operating
power in Tx-Rx FAST mode is 36.3mW at a 5.12Msps
clock frequency.
The Rx ADCs feature 54.9dB SINAD and 78dBc SFDR
at a 1.87MHz input frequency with a 7.5Msps sample
frequency. The analog I/Q input amplifiers are fully dif-
ferential and accept 1.024V
P-P
full-scale signals.
Typical I/Q channel matching is ±0.22° phase and
±0.02dB gain.
The Tx DACs with TD-SCDMA lowpass filters feature
-3dB cutoff frequency of 1.27MHz and >55dB stop-
band rejection at f
IMAGE
= 4.32MHz. The analog I/Q
full-scale output voltage range is selectable at ±410mV
or ±500mV. The output common-mode voltage is selec-
table from 0.9V to 1.4V and the I/Q channel offset is
adjustable. The typical I/Q channel matching is
±0.05dB gain and ±0.16° phase.
The Rx ADC and Tx DAC share a single, 10-bit parallel,
high-speed digital bus allowing half-duplex operation
for time-division duplex (TDD) applications. A 3-wire
serial interface controls power-management modes
and the aux-DAC channels.
The MAX19700 operates on a single +2.7V to +3.3V
analog supply and +1.8V to +3.3V digital I/O supply.
The MAX19700 is specified for the extended (-40°C to
+85°C) temperature range and is available in a 48-pin,
thin QFN package.
Pin Configuration
V
DD
DAC1
39
38
48
47
46
45
44
43
42
41
40
37
36
35
34
33
32
31
30
29
28
DAC2
REFN
QDP
QDN
V
DD
GND
IDP
IDN
TOP VIEW
COM
REFIN
Applications
TD-SCDMA Handsets
TD-SCDMA Data Cards
Portable Communication Equipment
REFP
V
DD
IAP
IAN
GND
CLK
GND
V
DD
QAN
QAP
V
DD
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
DAC3
N.C.
N.C.
V
DD
GND
V
DD
CS
SCLK
DIN
T/R
DR
SHDN
Ordering Information
PART*
MAX19700ETM
MAX19700ETM+
PIN-PACKAGE
48 Thin QFN-EP**
48 Thin QFN-EP**
PKG CODE
T4877-4
T4877-4
MAX19700
EXPOSED PADDLE (GND)
27
26
25
*All
devices are specified over the -40°C to +85°C operating
range.
**EP
= Exposed paddle.
+Denotes
lead-free package.
Functional Diagram appears at end of data sheet.
D1
D2
D3
D4
D5
OGND
OV
DD
D6
D0
THIN QFN
________________________________________________________________
Maxim Integrated Products
D7
D8
D9
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
7.5Msps, Ultra-Low-Power
Analog Front-End
MAX19700
ABSOLUTE MAXIMUM RATINGS
VDD to GND, OVDD to OGND ..............................-0.3V to +3.4V
GND to OGND.......................................................-0.3V to +0.3V
IAP, IAN, QAP, QAN, IDP, IDN, QDP,
QDN, REFP, REFN, REFIN, COM,
DAC1, DAC2, DAC3 to GND .................-0.3V to (VDD + 0.3V)
D0–D9, DR, T/R,
SHDN,
SCLK, DIN,
CS,
CLK to OGND .....................................-0.3V to (OVDD + 0.3V)
Continuous Power Dissipation (TA = +70°C)
48-Pin Thin QFN (derate 26.3mW/°C above +70°C) .......2.1W
Thermal Resistance
θ
JA ..................................................38°C/W
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
DD
= 3V, OV
DD
= 1.8V, internal reference (1.024V), C
L
≈
10pF on all digital outputs, f
CLK
= 7.5MHz (50% duty cycle), ADC input
amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, C
REFP
= C
REFN
= C
COM
=
0.33µF. Typical values are at T
A
= +25°C, unless otherwise noted. C
L
< 5pF on all aux-DAC outputs.) (Note 1)
PARAMETER
POWER REQUIREMENTS
Analog Supply Voltage
Output Supply Voltage
V
DD
OV
DD
Ext1-Tx, Ext3-Tx, and SPI2-Tx states;
transmit DAC operating mode (Tx),
f
CLK
= 5.12MHz, f
OUT
= 620kHz on both
channels; aux-DACs ON and at midscale
Ext2-Tx, Ext4-Tx, and SPI4-Tx states;
transmit DAC operating mode (Tx),
f
CLK
= 5.12MHz, f
OUT
= 620kHz on both
channels; aux-DACs ON and at midscale
Ext1-Rx, Ext4-Rx, and SPI3-Rx states;
receive ADC operating mode (Rx),
f
CLK
= 5.12MHz, f
IN
= 1.87MHz on both
channels; aux-DACs ON and at midscale
V
DD
Supply Current
Ext2-Rx, Ext3-Rx, and SPI1-Rx modes;
receive ADC operating mode (Rx),
f
CLK
= 5.12MHz, f
IN
= 1.87MHz on both
channels; aux-DACs ON and at midscale
Ext2-Tx, Ext4-Tx, and SPI4-Tx modes;
transmit DAC operating mode (Tx),
f
CLK
= 7.5MHz, f
OUT
= 620kHz on both
channels; aux-DACs ON and at midscale
Ext1-Tx, Ext3-Tx, and SPI2-Tx modes;
transmit DAC operating mode (Tx),
f
CLK
= 7.5MHz, f
OUT
= 620kHz on both
channels; aux-DACs ON and at midscale
6.6
2.7
1.8
3.0
3.3
V
DD
V
V
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
10.3
12.4
12.1
mA
13.1
16
10.4
2
_______________________________________________________________________________________
7.5Msps, Ultra-Low-Power
Analog Front-End
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 3V, OV
DD
= 1.8V, internal reference (1.024V), C
L
≈
10pF on all digital outputs, f
CLK
= 7.5MHz (50% duty cycle), ADC input
amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, C
REFP
= C
REFN
= C
COM
=
0.33µF. Typical values are at T
A
= +25°C, unless otherwise noted. C
L
< 5pF on all aux-DAC outputs.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
Ext1-Rx, Ext4-Rx, and SPI3-Rx modes;
receive ADC operating mode (Rx),
f
CLK
= 7.5MHz, f
IN
= 1.87MHz on both
channels; aux-DACs ON and at midscale
Ext2-Rx, Ext3-Rx, and SPI1-Rx modes;
receive ADC operating mode (Rx),
f
CLK
= 7.5MHz, f
IN
= 1.87MHz on both
channels; aux-DACs ON and at midscale
Standby mode, CLK = 0 or OV
DD
;
aux-DACs ON and at midscale
Idle mode, f
CLK
= 7.5MHz; aux-DACs ON
and at midscale
Shutdown mode, CLK = 0 or OV
DD
Ext1-Rx, Ext2-Rx, Ext3-Rx, Ext4-Rx,
SPI1-Rx, SPI3-Rx modes; receive ADC
operating mode (Rx), f
CLK
= 7.5MHz,
f
IN
= 1.87MHz on both channels;
aux-DACs ON and at midscale
Ext1-Tx, Ext2-Tx, Ext3-Tx, Ext4-Tx,
SPI2-Tx, SPI4-Tx modes; transmit DAC
operating mode (Tx), f
CLK
= 7.5MHz, f
OUT
= 620kHz; aux-DACs ON and at midscale
Idle mode, f
CLK
= 7.5MHz; aux-DACs ON
and at midscale
Shutdown mode, CLK = 0 or OV
DD
Standby mode, CLK = 0 or OV
DD
;
aux-DACs ON and at midscale
Rx ADC DC ACCURACY
Resolution
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Gain Error
DC Gain Matching
Offset Matching
Gain Temperature Coefficient
Power-Supply Rejection
PSRR
Offset error (V
DD
±5%)
Gain error (V
DD
±5%)
INL
DNL
Residual DC offset error
Include reference error
10
±0.85
±0.55
±0.5
±1.1
±0.01
±4.5
±15.7
±0.2
±0.04
±5
±5
±0.25
Bits
LSB
LSB
%FS
%FS
dB
LSB
ppm/°C
LSB
%FS
MIN
TYP
MAX
UNITS
MAX19700
12.8
16
V
DD
Supply Current
7
mA
2.7
4.7
0.7
4
6
µA
1.38
mA
OV
DD
Supply Current
72.9
10.9
0.01
0.03
µA
_______________________________________________________________________________________
3
7.5Msps, Ultra-Low-Power
Analog Front-End
MAX19700
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 3V, OV
DD
= 1.8V, internal reference (1.024V), C
L
≈
10pF on all digital outputs, f
CLK
= 7.5MHz (50% duty cycle), ADC input
amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, C
REFP
= C
REFN
= C
COM
=
0.33µF. Typical values are at T
A
= +25°C, unless otherwise noted. C
L
< 5pF on all aux-DAC outputs.) (Note 1)
PARAMETER
Rx ADC ANALOG INPUT
Input Differential Range
Input Common-Mode Voltage
Range
Input Impedance
Rx ADC CONVERSION RATE
Maximum Clock Frequency
Data Latency (Figure 3)
Rx ADC DYNAMIC CHARACTERISTICS (Note 3)
Signal-to-Noise Ratio
Signal-to-Noise Plus Distortion
Spurious-Free Dynamic Range
Third-Harmonic Distortion
Intermodulation Distortion
Third-Order Intermodulation
Distortion
Total Harmonic Distortion
Aperture Delay
Overdrive Recovery Time
Rx ADC INTERCHANNEL CHARACTERISTICS
Crosstalk Rejection
Amplitude Matching
Phase Matching
f
INX,Y
= 1.875MHz at -0.5dBFS, f
INX,Y
= 1MHz
at -0.5dBFS (Note 4)
f
IN
= 1.875MHz at -0.5dBFS (Note 5)
f
IN
= 1.875MHz at -0.5dBFS (Note 5)
-85
±0.02
±0.22
dB
dB
Degrees
1.5x full-scale input
SNR
SINAD
SFDR
HD3
IMD
IM3
THD
f
IN
= 1.875MHz, f
CLK
= 7.5MHz
f
IN
= 3.5MHz, f
CLK
= 7.5MHz
f
IN
= 1.875MHz, f
CLK
= 7.5MHz
f
IN
= 3.5MHz, f
CLK
= 7.5MHz
f
IN
= 1.875MHz, f
CLK
= 7.5MHz
f
IN
= 3.5MHz, f
CLK
= 7.5MHz
f
IN
= 1.875MHz, f
CLK
= 7.5MHz
f
IN
= 3.5MHz, f
CLK
= 7.5MHz
f
1
= 1.8MHz,
-7dBFS;
f
2
= 1MHz, -7dBFS
f
1
= 1.8MHz, -7dBFS;
f
2
= 1MHz, -7dBFS
f
IN
= 1.875MHz, f
CLK
= 7.5MHz
f
IN
= 3.5MHz, f
CLK
= 7.5MHz
66
53.6
53.7
55
54.8
54.9
54.7
78
70.1
-84
-72.1
-75.6
-78
-77.9
-71
3.5
2
-64
dB
dB
dBc
dBc
dBc
dBc
dBc
ns
ns
f
CLK
(Note 2)
Channel I
Channel Q
5
5.5
7.5
MHz
Clock
Cycles
V
ID
V
CM
R
IN
C
IN
Switched capacitor load
Differential or single-ended inputs
±0.512
V
DD
/ 2
720
5
V
V
kΩ
pF
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
4
_______________________________________________________________________________________
7.5Msps, Ultra-Low-Power
Analog Front-End
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 3V, OV
DD
= 1.8V, internal reference (1.024V), C
L
≈
10pF on all digital outputs, f
CLK
= 7.5MHz (50% duty cycle), ADC input
amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, C
REFP
= C
REFN
= C
COM
=
0.33µF. Typical values are at T
A
= +25°C, unless otherwise noted. C
L
< 5pF on all aux-DAC outputs.) (Note 1)
PARAMETER
Tx DAC DC ACCURACY
Resolution
Integral Nonlinearity
Differential Nonlinearity
Residual DC Offset
Full-Scale Gain Error
TRANSMIT-PATH DYNAMIC PERFORMANCE
Corner Frequency
Passband Ripple
Group Delay Variation in Passband
Error-Vector Magnitude
Stopband Rejection
EVM
3dB corner
DC to 640kHz (Note 6)
DC to 640kHz, guaranteed by design
DC to 700kHz
f
IMAGE
= 4.32MHz, f
OUT
= 800kHz,
f
CLK
= 5.12MHz
2MHz
4MHz
Baseband Attenuation
Spot relative to
100kHz
5MHz
10MHz
20MHz
DAC Conversion Rate
In-Band Noise Density
Third-Order Intermodulation
Distortion
Glitch Impulse
Spurious-Free Dynamic Range to
Nyquist
Total Harmonic Distortion to
Nyquist
Signal-to-Noise Ratio to Nyquist
SFDR
THD
SNR
f
CLK
= 7.5MHz, f
OUT
= 620kHz
f
CLK
= 7.5MHz, f
OUT
= 620kHz
f
CLK
= 7.5MHz, f
OUT
= 620kHz
60
f
CLK
N
D
IM3
(Note 2)
f
OUT
= 620kHz, f
CLK
= 5.12MHz,
offset = 500kHz
f
1
= 620kHz, f
2
= 640kHz
-121.7
76
10
76.5
-74.8
57.1
-59
55
20
46.5
54.7
81
88
7.5
MHz
dBc/Hz
dBc
pV
•
s
dBc
dB
dB
dB
1.1
1.27
0.28
50
2
1.5
0.5
100
MHz
dB
P-P
ns
%
dBc
N
INL
DNL
V
OS
Guaranteed monotonic (Note 6)
T
A
> +25°C
T
A
< +25°C
Include reference error (peak-to-peak error)
-4
-6.5
-50
10
±0.45
±0.26
±1
±1
+4
mV
+6.5
+50
mV
Bits
LSB
LSB
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MAX19700
_______________________________________________________________________________________
5
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