Si80xx-1kV
1
K
V
T
HREE
TO
S
I X
-C
HANNEL
D
IGITAL
I
SOLATORS
Default high or low output
Precise timing (typical)
Features
High-speed operation
DC
No start-up initialization required
Wide Operating Supply Voltage
3.15
to 10 Mbps
Transient Immunity 50 kV/µs
High electromagnetic immunity
AEC-Q100 qualification
Low power consumption (typical)
Wide temperature range
Up to 1000 V
RMS
isolation
– 5.5 V
ns propagation delay
20 ns pulse width distortion
100 ns minimum pulse width
40
Tri-state outputs with ENABLE
Schmitt trigger inputs
2.3
mA per channel at 10 Mbps
–40
RoHS-compliant packages
QSOP-16
to 125 °C
Ordering Information:
See page 18.
Applications
Industrial automation systems
Medical electronics
Hybrid electric vehicles
Isolated ADC, DAC
Power inverters
Communication systems
Description
Silicon Lab's family of low-power digital isolators are CMOS devices
offering substantial data rate, propagation delay, power, size, reliability,
and external BOM advantages over legacy isolation technologies. The
operating parameters of these products remain stable across wide
temperature ranges and throughout device service life for ease of
design and highly uniform performance. All device versions have
Schmitt trigger inputs for high noise immunity and only require VDD
bypass capacitors. Data rates up to 10 Mbps are supported, and all
devices achieve propagation delays of less than 65 ns. Enable inputs
provide a single point control for enabling and disabling output drive.
Ordering options include a choice of 1kV
RMS
isolation ratings.
Rev. 1.0 1/14
Copyright © 2014 by Silicon Laboratories
Si80xx-1kV
Si80xx
T
ABLE
Section
OF
C
ONTENTS
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.1. Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
3. Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3.1. Device Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.2. Undervoltage Lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.3. Layout Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.4. Fail-Safe Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4. Pin Descriptions (Si8030/35) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5. Pin Descriptions (Si8040/45) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6. Pin Descriptions (Si8050) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
7. Pin Descriptions (Si8055) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
8. Pin Descriptions (Si8065) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
9. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
10. Package Outline: 16-Pin QSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
11. Land Pattern: 16-Pin QSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
12. Top Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
12.1. Top Marking (16-Pin QSOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
12.2. Top Marking Explanation (16-Pin QSOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Rev. 1.0
3
Si80xx
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Ambient Operating Temperature*
Supply Voltage
Symbol
T
A
V
DD1
V
DD2
Min
–40
3.15
3.15
Typ
25
—
—
Max
125
5.5
5.5
Unit
ºC
V
V
*Note:
The maximum ambient temperature is dependent on data frequency, output loading, number of operating channels,
and supply voltage.
Table 2. Electrical Characteristics
Parameter
VDD Undervoltage
Threshold
VDD Undervoltage
Threshold
VDD Undervoltage
Threshold Hysteresis
Positive-Going Input
Threshold
Negative-Going
Input Threshold
Input Hysteresis
High Level Input Voltage
Low Level input voltage
High Level Output Voltage
Low Level Output Voltage
Input Leakage Current
Output Impedance
1
Enable Input High Current
Enable Input Low Current
Supply Current (DC)
V
DD1
V
DD2
Symbol
VDDUV+
VDDUV–
VDD
HYS
VT+
VT–
V
HYS
V
IH
V
IL
V
OH
V
OL
I
L
Z
O
I
ENH
I
ENL
(V
DD1
= 3.15 to 5.5 V, V
DD2
= 3.15 to 5.5 V, T
A
= –40 to 125 ºC)
Test Condition
V
DD1
, V
DD2
rising
V
DD1
, V
DD2
falling
Min
2.65
2.2
—
Typ
2.80
2.50
270
1.6
1.2
0.40
—
—
4.8
0.2
—
50
2.0
16
4.4
7.5
Max
3.05
2.75
—
1.9
1.4
—
—
0.8
—
0.4
±10
—
—
—
7.5
10
Unit
V
V
mV
V
V
V
V
V
V
V
µA
µA
µA
mA
mA
All inputs rising
All inputs falling
1.4
1.0
—
2.0
—
loh = –4 mA
lol = 4 mA
V
DD1
,V
DD2
–
0.4
—
—
—
V
ENx
= V
IH
V
ENx
= V
IL
V
I
=0, 1
C
L
= 15 pF
—
—
—
—
Notes:
1.
The nominal output impedance of an isolator driver channel is approximately 50
,
±40%, which is a combination of
the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2.
t
PSK(P-P)
is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3.
Start-up time is the time period from the application of power to valid data at the output.
4
Rev. 1.0
Si80xx
Table 2. Electrical Characteristics (Continued)
Parameter
Supply Current (10 Mbps)
V
DD1
V
DD2
Maximum Data Rate
Minimum Pulse Width
Propagation Delay
Pulse Width Distortion
|t
PLH
– t
PHL
|
Propagation Delay Skew
2
Channel-Channel Skew
Output Rise Time
Output Fall Time
Common Mode
Transient Immunity
Enable to Data Valid
Enable to Data Tri-State
Start-up Time
3
t
PHL
, t
PLH
PWD
t
PSK(P-P)
t
PSK
t
r
t
f
CMTI
t
en1
t
en2
t
SU
C
L
= 15 pF
See Figure 2
C
L
= 15 pF
See Figure 2
V
I
= V
DD
or 0 V
V
CM
= 1500 V (see Figure 3)
See Figure 1
See Figure 1
See Figure 2
See Figure 2
Symbol
(V
DD1
= 3.15 to 5.5 V, V
DD2
= 3.15 to 5.5 V, T
A
= –40 to 125 ºC)
Test Condition
V
I
= 5 MHz
C
L
= 15 pF
Min
—
—
0
—
20
—
—
—
—
—
35
—
—
—
Typ
4.4
9.4
—
—
40
20
20
20
2.5
2.5
50
10
10
40
Max
7.5
12
10
100
65
30
30
30
4.0
4.0
—
—
—
—
Unit
mA
mA
Mbps
ns
ns
ns
ns
ns
ns
ns
kV/µs
ns
ns
µs
Notes:
1.
The nominal output impedance of an isolator driver channel is approximately 50
,
±40%, which is a combination of
the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2.
t
PSK(P-P)
is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3.
Start-up time is the time period from the application of power to valid data at the output.
ENABLE
OUTPUTS
t
en1
t
en2
Figure 1. ENABLE Timing Diagram
Rev. 1.0
5
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