Femtoclock
®
Crystal-to-3.3V LVPECL
Frequency Synthesizer
Data Sheet
843002
G
ENERAL
D
ESCRIPTION
The 843002 is a two output LVPECL synthesizer optimized to
generate Fibre Channel reference clock frequencies . Using
a 26.5625MHz, 18pF parallel resonant crystal, the following
frequencies can be generated based on the 2 frequency select pins
(F_SEL[1:0]): 212.5MHz, 187.5MHz, 159.375MHz, 106.25MHz,
and 53.125MHz. The 843002 uses IDT’s 3
rd
generation low phase
noise VCO technology and can achieve 1ps or lower typical rms
phase jitter, easily meeting Fibre Channel jitter requirements. The
843002 is packaged in a small 20-pin TSSOP package.
F
EATURES
• Two 3.3V LVPECL outputs
• Selectable crystal oscillator interface
or LVCMOS/LVTTL single-ended input
• Supports the following output frequencies: 212.5MHz,
187.5MHz, 159.375MHz, 106.25MHz and 53.125MHz
• VCO range: 560MHz - 680MHz
• RMS phase jitter (637kHz - 10MHz): 0.72ps (typical)
• Typical phase noise at 212.5MHz
Phase noise:
Offset
Noise Power
100Hz ................-87.7 dBc/Hz
1KHz ..............-111.6 dBc/Hz
10KHz ..............-124.3 dBc/Hz
100KHz ..............-124.3 dBc/Hz
• Full 3.3V supply mode
• Lead-Free package RoHS compliant
• -30°C to 85°C ambient operating temperature
F
REQUENCY
S
ELECT
F
UNCTION
T
ABLE
Inputs
Input Fre-
quency
(MHz)
26.5625
26.5625
26.5625
26.5625
23.4375
F_SEL1
0
0
1
1
0
F_SEL0
0
1
0
1
0
M Divider
Value
24
24
24
24
24
N Divider
Value
3
4
6
12
3
M/N
Divider Value
8
6
4
2
8
Output
Frequency
(MHz)
212.5
159.375
106.25
53.125
187.5
P
IN
A
SSIGNMENT
843002
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm
package body
G Package
Top View
Q0
B
LOCK
D
IAGRAM
F_SEL[1:0]
Pulldown
nPLL_SEL
Pulldown
2
F_SEL[1:0]
TEST_CLK
Pulldown
26.5625MHz
nQ0
1
1
XTAL_IN
OSC
XTAL_OUT
nXTAL_SEL
Pulldown
0
Phase
Detector
VCO
637.5MHz
(w/26.5625MHz
Reference)
00
01
10
11
÷3
÷4
÷6
÷12
Q1
nQ1
0
M = 24 (fixed)
MR
Pulldown
©2016 Integrated Device Technology, Inc
1
Revision B January 21, 2016
843002 Data Sheet
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 7
2, 20
3, 4
5
Name
nc
V
CCO
Q0, nQ0
MR
Unused
Power
Ouput
Input
Type
Description
No connect.
Output supply pins.
Differential output pair. LVPECL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
causing the true outputs Qx to go low and the inverted outputs nQx
Pulldown
to go high. When logic LOW, the internal dividers and the outputs are en-
abled. LVCMOS/LVTTL interface levels.
Selects between the PLL and TEST_CLK as input to the dividers. When
Pulldown LOW, selects PLL (PLL Enable). When HIGH, deselects the reference clock
(PLL Bypass). LVCMOS/LVTTL interface levels.
Analog supply pin.
Pulldown Frequency select pins. LVCMOS/LVTTL interface levels.
Core supply pin.
Parallel resonant crystal interface. XTAL_OUT is the output,
XTAL_IN is the input.
Pulldown LVCMOS/LVTTL clock input.
Selects between crystal or TEST_CLK inputs as the the PLL Reference
Pulldown source. Selects XTAL inputs when LOW. Selects TEST_CLK when HIGH.
LVCMOS/LVTTL interface levels.
Negative supply pins.
Differential output pair. LVPECL interface levels.
6
8
9, 11
10, 16
12, 13
14
15
17
18, 19
nPLL_SEL
V
CCA
F_SEL0,
F_SEL1
V
CC
XTAL_OUT,
XTAL_IN
TEST_CLK
nXTAL_SEL
V
EE
nQ1, Q1
Input
Power
Input
Power
Input
Input
Input
Power
Output
NOTE:
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLDOWN
Parameter
Input Capacitance
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
Maximum
Units
pF
kΩ
©2016 Integrated Device Technology, Inc
2
Revision B January 21, 2016
843002 Data Sheet
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
73.2°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions
beyond those listed in the
DC Characteristics
or
AC Charac-
teristics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V±10%, TA = -30°C
TO
85°C
Symbol
V
CC
V
CCA
V
CCO
I
EE
I
CC
I
CCA
I
CCO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Core Supply Current
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
2.97
2.97
2.97
Typical
3.3
3.3
3.3
Maximum
3.63
3.63
3.63
135
100
15
31
Units
V
V
V
mA
mA
mA
mA
T
ABLE
3B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V±10%, TA = -30°C
TO
85°C
Symbol
V
IH
V
IL
Parameter
Input High Voltage
nPLL_SEL, nXTAL_SEL,
Input
F_SEL0, F_SEL1, MR
Low Voltage
TEST_CLK
TEST_CLK, MR,
Input
F_SEL0, F_SEL1,
High Current
nPLL_SEL, nXTAL_SEL,
TEST_CLK, MR,
Input
F_SEL0, F_SEL1,
Low Current
nPLL_SEL, nXTAL_SEL,
Test Conditions
Minimum
2
-0.3
-0.3
V
CC
= V
IN
= 3.63V
Typical
Maximum
V
CC
+ 0.3
0.8
1.0
150
Units
V
V
V
µA
I
IH
I
IL
V
CC
= 3.63V, V
IN
= 0V
-150
µA
T
ABLE
3C. LVPECL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V±10%, TA = -30°C
TO
85°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
V
CCO
- 1.4
V
CCO
- 2.0
0.6
Typical
Maximum
V
CCO
- 0.9
V
CCO
- 1.7
1.0
Units
V
V
V
NOTE 1: Outputs terminated with 50Ω to V
CCO
- 2V.
©2016 Integrated Device Technology, Inc
3
Revision B January 21, 2016
843002 Data Sheet
T
ABLE
4. C
RYSTAL
C
HARACTERISTICS
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
NOTE: Characterized using an 18pF parallel resonant crystal.
23.33
Test Conditions
Minimum
Typical
26.5625
Maximum
28.33
50
7
Units
MHz
Ω
pF
Fundamental
T
ABLE
5. AC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V±10%, TA = -30°C
TO
85°C
Symbol
Parameter
Test Conditions
F_SEL[1:0] = 00
f
OUT
Output Frequency
F_SEL[1:0] = 01
F_SEL[1:0] = 10
F_SEL[1:0] =11
tsk(o)
Output Skew; NOTE 1, 2
212.5MHz, (637KHz - 10MHz)
tjit(Ø)
RMS Phase Jitter (Random);
NOTE 3
Output Rise/Fall Time
Output Duty Cycle
159.375MHz, (637KHz - 10MHz)
106.25MHz, (637KHz - 10MHz)
53.125MHz, (637KHz - 10MHz)
t
R
/ t
F
odc
20% to 80%
F_SEL[1:0] =00
300
46
0.72
0.76
0.84
0.97
600
54
51
Minimum
186.67
140
93.33
46.67
Typical
Maximum
226.67
170
113.33
56.67
20
Units
MHz
MHz
MHz
MHz
ps
ps
ps
ps
ps
ps
%
%
F_SEL[1:0] ¹ 00
49
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at V
CCO
/2.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: See Phase Noise plot.
©2016 Integrated Device Technology, Inc
4
Revision B January 21, 2016
843002 Data Sheet
T
YPICAL
P
HASE
N
OISE AT
53.125MH
Z
0
-10
-20
-30
-40
-50
-60
53.125MHz
N
OISE
P
OWER
dBc
Hz
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
10
100
1k
➤
RMS Phase Jitter (Random)
637Khz to 10MHz = 0.97ps (typical)
Fibre Channel Jitter Filter
Raw Phase Noise Data
➤
10k
T
YPICAL
P
HASE
N
OISE AT
106.25MH
Z
0
-10
-20
-30
-40
-50
-60
N
OISE
P
OWER
dBc
Hz
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
10
100
1k
➤
➤
➤
Phase Noise Result by adding
Fibre Channel Filter to raw data
100k
1M
10M
100M
O
FFSET
F
REQUENCY
(H
Z
)
106.25MHz
RMS Phase Jitter (Random)
637Khz to 10MHz = 0.84ps (typical)
Fibre Channel Jitter Filter
Raw Phase Noise Data
➤
Phase Noise Result by adding
Fibre Channel Filter to raw data
100k
1M
10M
100M
10k
O
FFSET
F
REQUENCY
(H
Z
)
©2016 Integrated Device Technology, Inc
5
Revision B January 21, 2016
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