Low Skew, 1-to-9
LVCMOS Fanout Buffer
Data Sheet
83947
G
ENERAL
D
ESCRIPTION
The 83947I is a low skew, 1-to-9 LVCMOS Fanout Buffer. The low
impedance LVCMOS/LVTTL outputs are designed to drive 50Ω series
or parallel terminated transmission lines. The effective fanout can be
increased from 9 to 18 byutilizing the ability of the outputs to drive two
series terminated lines.
Guaranteed output and part-to-part skew characteristics make the
83947I ideal for high performance, single ended applications that also
require a limited output voltage.
F
EATURES
•
9 LVCMOS/LVTTL outputs
•
Selectable CLK0 and CLK1 can accept the following
input levels: LVCMOS and LVTTL
•
Maximum output frequency: 110MHz
•
Output skew: 500ps (maximum)
•
Part-to-part skew: 2ns (maximum)
•
3.3V operating supply
•
-40°C to 85°C ambient operating temperature
•
Lead-Free package available
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
V
DDO
V
DDO
GND
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
GND
V
DDO
Q8
GND
Q7
V
DDO
Q6
GND
GND
GND
Q0
Q1
Q2
32 31 30 29 28 27 26 25
GND
CLK_SEL
CLK0
CLK1
CLK_EN
OE
V
DD
GND
24
23
22
GND
Q3
V
DDO
Q4
GND
Q5
V
DDO
GND
ICS83947I
21
20
19
18
17
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
©2016 Integrated Device Technology, Inc
1
Revision B March 17, 2016
83947 Data Sheet
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 8, 9, 12, 16, 17, 20,
24, 25, 29, 32
2
3, 4
5
6
7
Name
GND
CLK_SEL
CLK0, CLK1
CLK_EN
OE
V
DD
Type
Power
Input
Input
Input
Input
Power
Pullup
Power supply ground.
Clock select input. When HIGH, selects CLK1. When LOW,
selects CLK0. LVCMOS / LVTTL interface levels.
Pullup Reference clock inputs. LVCMOS / LVTTL interface levels.
Pullup Clock enable. LVCMOS / LVTTL interface levels.
Pullup Output enable. LVCMOS / LVTTL interface levels.
Coree supply pin.
Description
10, 14, 18, 22, 27, 31
V
DDO
Power
Output supply pins.
11, 13, 15, 19, 21, 23, Q8, Q7, Q6, Q5, Q4,
Q0 thru Q8 clock outputs.
Output
26, 28, 30
Q3, Q2, Q1, Q0
LVCMOS / LVTTL interface levels.
NOTE:
Pullup
refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
C
PD
R
PULLUP
R
PULLDOWN
R
OUT
Parameter
Input Capacitance
Power Dissipation Capacitance
(per output)
Input Pullup Resistor
Input Pulldown Resistor
Output Impedance
5
Test Conditions
Minimum
Typical
4
25
51
51
7
12
Maximum
Units
pF
pF
KΩ
KΩ
Ω
T
ABLE
3. O
UTPUT
E
NABLE AND
C
LOCK
E
NABLE
F
UNCTION
T
ABLE
Control Inputs
OE
0
1
1
CLK_EN
X
0
1
Output
Q0:Q8
Hi-Z
LOW
Follows CLK input
©2016 Integrated Device Technology, Inc
2
Revision B March 17, 2016
83947 Data Sheet
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
DD
+ 0.5 V
-0.5V to V
DDO
+ 0.5V
47.9°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions
beyond those listed in the
DC Characteristics
or
AC Charac-
teristics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V±0.3V, T
A
= -40°C
TO
85°C
Symbol
V
DD
V
DDO
I
DD
Parameter
Coret Supply Voltage
Output Supply Voltage
Input Supply Current
Test Conditions
Minimum
3.0
3.0
Typical
3.3
3.3
33
Maximum
3.6
3.6
50
Units
V
V
mA
T
ABLE
4B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V±0.3V, T
A
= -40°C
TO
85°C
Symbol
V
IH
V
IL
I
IN
V
OH
V
OL
Parameter
Input High Voltage
Input Low Voltage
Input Current
CLK0, CLK1, CLK_SEL,
OE, CLK_EN
I
OH
= -20mA
I
OL
= 20mA
-100
2.5
0.4
Test Conditions
Minimum
2
Typical
Maximum
3.6
0.8
Units
V
V
µA
V
V
Output High Voltage
Output Low Voltage
©2016 Integrated Device Technology, Inc
3
Revision B March 17, 2016
83947 Data Sheet
T
ABLE
5. AC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V±0.3V, T
A
= -40°C
TO
85°C
Symbol
f
MAX
t
PD
tsk(o)
tsk(pp)
t
PW
t
S
t
H
t
ZL
, t
ZH
t
LZ
, t
HZ
t
R
t
F
Parameter
Output Frequency
Propagation Delay, NOTE 1
Output Skew; NOTE 2, 5
Part-to-Part Skew; NOTE 3, 5
Output Pulse Width
Clock Enable Setup Time; NOTE 6
Clock Enable Hold Time; NOTE 6
Output Enable Time; NOTE 4
Output Disable Time; NOTE 4
Output Rise Time
Output Fall Time
0.8V to 2.0V
0.8V to 2.0V
0.2
0.2
CLK_EN to CLK
CLK_EN to CLK
Test Conditions
CLK to Q
Measured on
rising edge @V
DDO
/2
Measured on
rising edge @V
DDO
/2
tPeriod/2 - 800
0
1
11
11
1
1
Minimum
110
1.8
Typical
Maximum
4.5
500
2
tPeriod/2 + 800
Units
MHz
ns
ps
ns
ps
ns
ns
ns
ns
ns
ns
All parameters measured at f
MAX
unless noted otherwise.
NOTE 1: Measured from V
DD
/2 of the input to V
DDO
/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at V
DDO
/2.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with
equal load conditions. Using the same type of inputs on each device, the outputs are measured at V
DDO
/2.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 6: Setup and Hold times are relative to the rising edge of the input clock.
©2016 Integrated Device Technology, Inc
4
Revision B March 17, 2016
83947 Data Sheet
P
ARAMETER
M
EASUREMENT
I
NFORMATION
3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
O
UTPUT
S
KEW
P
ART
-
TO
-P
ART
S
KEW
P
ROPAGATION
D
ELAY
O
UTPUT
R
ISE
/F
ALL
T
IME
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
©2016 Integrated Device Technology, Inc
5
Revision B March 17, 2016
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