Low Skew, 1-to-10, HSTL Fanout Buffer
ICS83210
DATA SHEET
G
ENERAL
D
ESCRIPTION
The ICS83210 is a low skew, 1-to-10 HSTL Fanout Buffer.
The class II HSTL outputs are balanced push-pull in design,
capable of delivering 16mA into a 10pF load. This class allows
both source series termination and symmetrically double par-
allel termination.
F
EATURES
•
Ten single-ended HSTL outputs
•
One single-ended HSTL clock input
•
Maximum input frequency: 150MHz
•
Output skew: 110ps (maximum)
•
Part-to-part skew: 2ns (maximum)
•
1.5V power supply
•
0°C to 85°C ambient operating temperature
•
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
B
LOCK
D
IAGRAM
Q0
Q1
IN
Q8
Q9
nOE
Pulldown
P
IN
A
SSIGNMENT
GND
32 31 30 29 28 27 26 25
V
DD
GND
V
DD
nOE
GND
IN
V
DD
GND
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
GND
GND
Q9
V
DD
V
DD
Q8
Q7
GND
32-Lead TQFP
7mm x 7mm x 1.0mm package body
Y package
Top View
GND
GND
V
DD
V
DD
ICS83210
Q0
ICS83210AY REVISION A SEPTEMBER 9, 2010
1
©2010
Integrated Device Technology, Inc.
Q1
Q2
24
23
22
21
20
19
18
17
GND
Q3
Q4
V
DD
V
DD
Q5
Q6
GND
ICS83210 Data Sheet
LOW SKEW, 1-TO-10, HSTL FANOUT BUFFER
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 3, 7, 12, 13,
20, 21, 28, 29
2, 5, 8, 9, 10,
16, 17, 24, 25, 31, 32
4
Name
V
DD
GND
nOE
Power
Power
Input
Type
Description
Power supply pins.
Power supply ground.
Output enable/disable input pin. When LOW, outputs Qx outputs are
Pulldown enabled. When HIGH, Qx outputs are disabled low.
LVCMOS/LVTTL interface levels.
Single-ended reference clock input. HSTL interface levels.
5
IN
Input
Q9, Q8, Q7,
11, 14, 15,
Q6, Q5, Q4,
Output
Single-ended HSTL clock outputs.
18, 19, 22,
Q3, Q2, Q1, Q0
23, 26, 27, 30
NOTE:
Pulldown
refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLDOWN
C
OUT
R
OUT
Parameter
Input Capacitance
Input Pulldown Resistor
Output Pin Capacitance
Output Impedance
Test Conditions
Minimum
Typical
4
51
4.5
20
6
Maximum
Units
pF
kΩ
pF
Ω
ICS83210AY REVISION A SEPTEMBER 9, 2010
2
©2010
Integrated Device Technology, Inc.
ICS83210 Data Sheet
LOW SKEW, 1-TO-10, HSTL FANOUT BUFFER
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Storage Temperature, T
STG
4.6V
-0.5V to V
DD
+ 0.5 V
-0.5V to V
DD
+ 0.5V
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute Maximum
Ratings may cause permanent damage to the device. These rat-
ings are stress specifications only. Functional operation of prod-
uct at these conditions or any conditions beyond those listed in
the
DC Characteristics
or
AC Characteristics
is not implied.
Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Package Thermal Impedance,
θ
JA
75.5°C/W (0 mps)
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 1.5V ± 8%, T
A
= 0°C
TO
85°C
Symbol
V
DD
I
DD
I
DDQ
Parameter
Power Supply Voltage
Power Supply Current
Quiescent Supply Current
Outputs Loaded @ 62.5MHz
V
IN
= 0V, outputs disabled
Test Conditions
Minimum
1.38
Typical
1.5
21 5
Maximum
1.62
250
1
Units
V
mA
mA
T
ABLE
3B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
DD
= 1.5V ± 8%, T
A
= 0°C
TO
85°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
nOE
nOE
nOE
nOE
-5
Test Conditions
Minimum
0.7*V
DD
-0.3
Typical
Maximum
V
DD
+ 0.3
0.3*V
DD
150
Units
V
V
µA
µA
T
ABLE
3C. HSTL DC C
HARACTERISTICS
,
V
DD
= 1.5V ± 8%, T
A
= 0°C
TO
85°C
Symbol
V
IH
V
IL
V
OH
V
OL
Parameter
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
IN
IN
Test Conditions
V
REF
= 0.75V
I
OH
= -16mA
I
OL
= 16mA
Minimum
0.85
-0.3
1.0
-0.3
Typical
Maximum
1.8
0.65
V
DD
+ 0.3
0. 4
Units
V
V
V
V
ICS83210AY REVISION A SEPTEMBER 9, 2010
3
©2010
Integrated Device Technology, Inc.
ICS83210 Data Sheet
LOW SKEW, 1-TO-10, HSTL FANOUT BUFFER
T
ABLE
4. AC C
HARACTERISTICS
,
V
DD
= 1.5V ± 8%, T
A
= 0°C
TO
85°C
Symbol
f
IN
t
PLH
t
PHL
Parameter
Input Frequency
Propagation Delay, Low-to-High; NOTE 1
Propagation Delay, High-to-Low NOTE 1
Output Skew; NOTE 2, 4
Par t-to-Par t Skew; NOTE 3, 4
Output Enable Time
Output Disable Time
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
Fout
≤
100MHz
250
48
1.0
1.0
Test Conditions
Minimum
Typical
Maximum
150
5. 5
5.5
110
2
7
7
1.3
52
Units
MHz
ns
ns
ps
ns
ns
ns
ns
%
t
sk(o)
t
sk(pp)
t
EN
t
DIS
t
R
/ t
F
o dc
Fout > 100MHz
45
55
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the
device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after
thermal equilibrium has been reached under these conditions.
NOTE 1: Measured from the V
DD
/2 of the input to V
DD
/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V
DD
/2 of the
output.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same
frequency and with equal load conditions at the same temperature. Using the same type of inputs on each device, the outputs are
measured at V
DD
/2 of the output.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
ICS83210AY REVISION A SEPTEMBER 9, 2010
4
©2010
Integrated Device Technology, Inc.
ICS83210 Data Sheet
LOW SKEW, 1-TO-10, HSTL FANOUT BUFFER
P
ARAMETER
M
EASUREMENT
I
NFORMATION
0.75V±8%
PART 1
V
DD
SCOPE
Qx
Qx
V
DD
2
PART 2
V
DD
HSTL
GND
Qy
2
tsk(pp)
-0.75V±8%
1.5V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
P
ART
-
TO
-P
ART
S
KEW
V
Qx
DD
V
DD
V
DD
2
V
DD
V
DD
2
tp
HL
2
IN
2
V
Qy
Q0:Q9
DD
2
tsk(o)
2
tp
LH
O
UTPUT
S
KEW
P
ROPAGATION
D
ELAY
V
DD
80%
20%
Q0:Q9
80%
20%
Q0:Q9
2
t
PW
t
PERIOD
t
R
t
F
odc =
t
PW
t
PERIOD
x 100%
O
UTPUT
R
ISE
/F
ALL
T
IME
ICS83210AY REVISION A SEPTEMBER 9, 2010
5
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
©2010
Integrated Device Technology, Inc.
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