DATASHEET
LOCO™ PLL CLOCK GENERATOR
Description
The ICS514 LOCO
TM
is the most cost effective way to
generate a high-quality, high-frequency clock output
from a 14.31818 MHz crystal or clock input. The name
LOCO stands for Low Cost Oscillator, as it is designed
to replace crystal oscillators in most electronic
systems. Using Phase-Locked Loop (PLL) techniques,
the device uses a standard, inexpensive crystal to
produce output clocks up to 66.66 MHz.
Stored in the chip’s ROM is the ability to generate five
different output frequencies, allowing one chip to work
in different speed processor systems.
The device also has a power-down mode that turns off
the clock outputs when both select pins are low. In this
mode, the internal PLL is not running.
ICS514
Features
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Packaged as 8-pin SOIC or die
Pb (lead) free package
IDT’s lowest cost PLL clock plus reference
Produces common computer frequencies
Input crystal frequency typically 14.3182 MHz
Output clock frequencies up to 66.66 MHz from a
14.3182 MHz crystal or input clock
Low jitter of 50 ps (one sigma)
Compatible with all popular CPUs
Duty cycle of 45/55
Custom frequencies available
Operating voltage of 3.3 V to 5.5 V
Power-down mode turns off chip
25 mA drive capability at TTL levels
Advanced, low-power CMOS process
Block Diagram
VDD
S1:0
2
PLL Clock
Synthesis
and Control
Circuitry
Crystal
Oscillator
CLK
X1/ICLK
14.31818 MHz crystal
or clock input
X2
REF
Optional crystal capacitors
GND
IDT™ / ICS™
LOCO™ PLL CLOCK GENERATOR
1
ICS514
REV G 051310
ICS514
LOCO™ PLL CLOCK GENERATOR
CLOCK MULTIPLIER
Pin Assignment
X1/ I CLK
VDD
GND
REF
1
2
3
4
8
7
6
5
X2
S1
S0
CLK
Clock Decoding Table (MHz) with 14.31818
MHz Crystal or Clock Input
S1
0
0
M
M
1
1
S0
0
1
0
1
0
1
CLK
Power-down CLK
25
33.33
40
50
66.66
Multiplier
—
1.746
2.328
2.794
3.492
4.656
Accuracy
—
1 ppm
0.008%
1 ppm
1 ppm
0.008%
8 - p i n ( 1 5 0 mi l ) S OI C
0 = connect directly to ground
1 = connect directly to VDD
M = leave unconnected (floating)
CLK and REF stop low in power-down state
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
Pin
Name
XI/ICLK
VDD
GND
REF
CLK
S0
S1
X2
Pin
Type
Input
Power
Power
Output
Output
Tri-level Input
Tri-level Input
Output
Pin Description
Crystal connection to a 14.31818 MHz crystal or clock input.
Connect to +3.3 V or +5 V.
Connect to ground.
Reference 14.31818 MHz crystal oscillator buffered clock output.
Clock output per table above.
Select 0 for output clock. Connect to GND or VDD or float. See
table above.
Select 1 for output clock. Connect to GND or VDD or float. See
table above.
Crystal connection to a 14.31818 MHz crystal. Leave unconnected
for clock input.
Notes:
1. With S1 = S0 = 0, the internal PLL is turned off and the CLK outputs stops low. The crystal oscillator and
REF output are still active.
2. With a clock input, the phase relationship between the input and the output clocks can change each time
the device is powered on. If a fixed phase relationship is required, use the ICS571 or other zero delay
multipliers.
IDT™ / ICS™
LOCO™ PLL CLOCK GENERATOR
2
ICS514
REV G 051310
ICS514
LOCO™ PLL CLOCK GENERATOR
CLOCK MULTIPLIER
External Components
Decoupling Capacitor
As with any high-performance mixed-signal IC, the
ICS514 must be isolated from system power supply
noise to perform optimally.
A decoupling capacitor of 0.01µF must be connected
between VDD and the GND. It must be connected close
to the ICS514 to minimize lead inductance. No external
power supply filtering is required for the ICS514.
X2 to ground. These capacitors are used to adjust the
stray capacitance of the board to match the nominally
required crystal load capacitance. Because load
capacitance can only be increased in this trimming
process, it is important to keep stray capacitance to a
minimum by using very short PCB traces (and no vias)
between the crystal and device. Crystal capacitors, if
needed, must be connected from each of the pins X1
and X2 to ground.
The value (in pF) of these crystal caps should equal (C
L
-12 pF)*2. In this equation, C
L
= crystal load capacitance
in pF. Example: For a crystal with a 16 pF load
capacitance, each crystal capacitor would be 8 pF
[(16-12) x 2 = 8].
Series Termination Resistor
A 33Ω terminating resistor can be used next to the CLK
and REF pins for trace lengths over one inch.
Crystal Load Capacitors
The total on-chip capacitance is approximately 12 pF. A
parallel resonant, fundamental mode crystal should be
used. The device crystal connections should include
pads for small capacitors from X1 to ground and from
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS514. These ratings, which
are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the
device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Supply Voltage, VDD
All Inputs and Outputs (referenced to GND)
Ambient Operating Temperature
Storage Temperature
Soldering Temperature
7V
Rating
-0.5 V to VDD+0.5 V
0 to +70° C
-65 to +150° C
260° C
IDT™ / ICS™
LOCO™ PLL CLOCK GENERATOR
3
ICS514
REV G 051310
ICS514
LOCO™ PLL CLOCK GENERATOR
CLOCK MULTIPLIER
Recommended Operation Conditions
Parameter
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
Min.
0
+3.0
Typ.
Max.
+70
+5.5
Units
°
C
V
DC Electrical Characteristics
VDD=5.0 V ±5%
, Ambient temperature 0 to +70° C, unless stated otherwise
Parameter
Operating Voltage
Input High Voltage, ICLK only
Input Low Voltage, ICLK only
Input High Voltage
Input Low Voltage
Input High Voltage
Input Mid Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
IDD Operating Supply Current
IDD Power-down Supply
Current, 3.3 V
Short Circuit Current
On-Chip Pull-up Resistor
Input Capacitance, S1, S0
Symbol
VDD
V
IH
V
IL
V
IH
V
IL
V
IH
V
IM
V
IL
V
OH
V
OL
Conditions
ICLK (pin 1)
ICLK (pin 1)
S0
S0
S1
S1
S1
I
OH
= -25 mA
I
OL
= 25 mA
No load, 66.66
MHz
S1=S0=0
CLK output
Pin 6
Pins 6, 7
Min.
3.0
(VDD/2)+1
2.0
Typ.
VDD/2
VDD/2
Max.
5.5
(VDD/2)-1
0.8
Units
V
V
V
V
V
V
V
VDD-0.5
VDD/2
0.5
2.4
0.4
20
1.5
+70
270
4
V
V
V
mA
mA
mA
kΩ
pF
AC Electrical Characteristics
VDD = 5.0 V ±5%,
Ambient Temperature 0 to +70° C, unless stated otherwise
Parameter
Input Frequency, crystal input
Input Frequency, clock input
Output Frequency, VDD = 4.5 to 5.5 V
Output Frequency, VDD = 3.0 to 3.6 V
Output Clock Rise Time
Output Clock Fall Time
Output Clock Duty Cycle
Symbol
F
IN
F
IN
F
OUT
F
OUT
t
OR
t
OF
t
OD
Conditions
Min.
5
2
14
14
Typ.
14.31818
14.31818
66.66
66.66
1
1
Max.
27
50
140
100
Units
MHz
MHz
MHz
MHz
ns
ns
0.8 to 2.0 V
2.0 to 8.0 V
1.5 V,up to 140 MHz
45
49-51
55
%
IDT™ / ICS™
LOCO™ PLL CLOCK GENERATOR
4
ICS514
REV G 051310
ICS514
LOCO™ PLL CLOCK GENERATOR
CLOCK MULTIPLIER
Parameter
Power-up time, from PD to outputs
stable
Power-down time, from running to PD
state
Absolute Clock Period Jitter
One Sigma Clock Period Jitter
Symbol
Conditions
Min.
Typ.
5
Max.
10
50
Units
ms
ns
ps
ps
t
ja
t
js
Deviation from
mean
+160
50
Thermal Characteristics
Parameter
Thermal Resistance Junction to
Ambient
Symbol
θ
JA
θ
JA
θ
JA
θ
JC
Conditions
Still air
1 m/s air flow
3 m/s air flow
Min.
Typ.
150
140
120
40
Max. Units
°
C/W
°
C/W
°
C/W
°
C/W
Thermal Resistance Junction to Case
Marking Diagram
8
5
514MLF
YYWW
######
1
4
Notes:
1. ###### is the lot code.
2. YYWW is the last two digits of the year and the week.
3. “LF” designates Pb (lead) fee package.
IDT™ / ICS™
LOCO™ PLL CLOCK GENERATOR
5
ICS514
REV G 051310
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