MCP2021A/2A
LIN Transceiver with Voltage Regulator
Features
• The MCP2021A/2A is compliant with:
- LIN Bus Specifications Version 1.3, and 2.x.
- SAE J2602-2
• Support Baud Rates up to 20 kBaud
• 43V Load Dump Protected
• Maximum Continuous Input Voltage of 30V
• Wide LIN Compliant Supply Voltage, 6.0 - 18.0V
• Extended Temperature Range: -40 to +125°C
• Interface to PIC
®
EUSART and Standard USARTs
• Wake-up on LIN Bus Activity or Local Wake Input
• LIN Bus Pin
- Internal Pull-up Termination Resistor and
Diode for Slave Node
- Protected Against V
BAT
Shorts
- Protected Against Loss of Ground
- High Current Drive
• TXD and LIN Bus Dominant Time-out Function
• Two Low-Power Modes
- TRANSMITTER OFF Mode: 9 µA (typical)
- POWER DOWN Mode: 4.5µA (typical)
• Output Indicating Internal RESET State (POR or
SLEEP Wake)
• MCP2021A/2A On-chip Voltage Regulator
- Output Voltage of 5.0V or 3.3V 70 mA
Capability withTolerances of ±3% Over
Temperature Range
- Internal Short Circuit Current Limit
- Only External Filter and Load Capacitors
Needed
• Automatic Thermal Shutdown
• High Electromagnetic Immunity (EMI), Low Elec-
tromagnetic Emission (EME)
• Robust ESD Performance: ±15 kV for LBUS and
VBB pin (IEC61000-4-2)
• Transient Protection for LBUS and VBB Pins in
Automotive Environment (ISO7637)
• Meets Stringent Automotive Design Requirements
Including “OEM Hardware Requirements for LIN,
CAN and FlexRay Interfaces in Automotive Appli-
cations”, Version 1.2, March 2011
• Multiple Package Options Including Small
4x4 mm DFN
Description
The MCP2021A/2A provides a bidirectional, half-
duplex communication physical interface to meet the
LIN bus specification Revision 2.1 and SAE J2602-2.
The device incorporates a voltage regulator with 5V or
3.3V 70 mA regulated power supply output. The device
has been designed to meet the stringent quiescent
current requirements of the automotive industry and
will survive +43V load dump transients, and double
battery jumps.
Package Types (Top View)
MCP2021A
PDIP, SOIC
RXD
CS/LWAKE
VREG
TXD
1
2
3
4
8
7
6
5
FAULT/TXE
V
BB
L
BUS
V
SS
MCP2021A
4x4 DFN
RXD 1
CS/LWAKE 2
VREG 3
TXD 4
EP
9
8 FAULT/TXE
7 V
BB
6 L
BUS
5 V
SS
MCP2022A
PDIP, SOIC, TSSOP
RXD
CS/LWAKE
VREG
TXD
RESET
NC
NC
1
2
3
4
5
6
7
14
13
12
11
10
9
8
FAULT/TXE
V
BB
L
BUS
V
SS
NC
NC
NC
* Includes Exposed Thermal Pad (EP).
2012 Microchip Technology Inc.
DS22298A-page 1
MCP2021A/2A
Block Diagram
V
REG
Short Circuit
Protection
Thermal
Protection
Voltage
Regulator
RESET
(MCP2022A ONLY)
V
BB
Ratiometric
Reference
Bus Wakeup
V
REG
Internal Circuits 4.2V
V
REG
Wake-Up
Logic and
Power Control
RXD
CS/LWAKE
TXD
FAULT/TXE
Bus
Dominant
Timer
Slope Control
~30
k
L
BUS
V
SS
Thermal
and
Short Circuit
Protection
MCP2021A/2A Family Members
Device
MCP2021A-500
MCP2021A-330
MCP2022A-500
MCP2022A-330
Package
8-PIN DFN, SOIC, PDIP
8-PIN DFN, SOIC, PDIP
14-PIN SOIC, TSSOP, PDIP
14-PIN SOIC, TSSOP, PDIP
Regulator Output Voltage
5.0V
3.3V
5.0V
3.3V
RESET Pin
No
No
Yes
Yes
DS22298A-page 2
2012 Microchip Technology Inc.
MCP2021A/2A
1.0
FUNCTION DESCRIPTION
1.1
Modes of Operation
The MCP2021A/2A provides a physical interface
between a microcontroller and a LIN half-duplex bus. It
is intended for automotive and industrial applications
with serial bus baud rates up to 20 Kbaud. This device
will translate the CMOS/TTL logic levels to LIN logic
levels, and vice versa. The device offers optimum EMI
and ESD performance; it can withstand high voltage on
the LIN bus. The device supports two low-power
modes to meet automotive industry power consump-
tion requirements. The MCP2021A/2A also provides a
+5V or 3.3V 70 mA regulated power output.
The MCP2021A/2A works in five modes: POWER-ON-
RESET mode, POWER-DOWN mode, READY mode,
OPERATION mode, and TRANSMITTER OFF mode.
For an overview of all operational modes, please refer
to
Table 1-1.
For the operational mode transition,
please refer to
Figure 1-1.
FIGURE 1-1:
STATE DIAGRAM
CS/LWAKE=0
POR
(2)
VREG OFF
RX OFF
TX OFF
VBB>V
ON
READY
VREG ON
RX ON
TX OFF
CS/LWAKE=1&
FAULT/TXE=0&
VREG_OK=1
(1)
CS/LWAKE=1 &
FAULT/TXE=1
(3)
&
TXD=1&
VREG_OK=1
(1)
CS/LWAKE=1 OR
Voltage Rising Edge on LBUS
TX OFF
VREG ON
RX ON
TX OFF
CS/LWAKE=0
CS/LWAKE=1&
FAULT/TXE=1
(3)
&
TXD=1
OPERATION
VREG ON
RX ON
TX ON
CS/LWAKE=1&
FAULT/TXE=0
POWER-DOWN
VREG OFF
RX OFF
TX OFF
CS/LWAKE=0
Note 1:
VREG_OK : Regulator Output Voltage > 0.8V
REG_NOM.
2:
If the voltage on pin VBB falls below V
OFF
, the device will enter POWER ON RESET mode from all other
modes, which is not shown in the figure.
3:
FAULT/TXE = 1 represents input high and no fault conditions. FAULT/TXE = 0 represents input low or a
fault condition, Refer to
Table 1-3.
1.1.1
POWER-ON-RESET MODE
Upon application of V
BB
, or whenever the voltage on
VBB is below the threshold of regulator turn off voltage
V
OFF
(typically 4.50V), the device enters POWER-ON-
RESET mode (POR). During this mode, the device
maintains the digital section in a reset mode and waits
until the voltage on V
BB
pin rises above the threshold of
regulator turn on voltage V
ON
(typically 5.75V) to enter
to the READY mode. In POWER-ON-RESET mode,
the LIN physical layer and voltage regulator are dis-
abled, and RESET output (MCP2022A only) is forced
to LOW.
2012 Microchip Technology Inc.
DS22298A-page 3
MCP2021A/2A
1.1.2
READY MODE
The device enters READY mode from POR mode after
the voltage on VBB rises above the threshold of
regulator turn on voltage V
ON
or from POWER-DOWN
mode when a remote or local wake-up event happens.
Upon entering READY mode, the voltage regulator and
receiver section of the transceiver are powered up. The
transmitter remains in an off state. The device is ready
to receive data but not to transmit. In order to minimize
the power consumption, the regulator operates in a
reduced power mode. It has a lower GBW product and
thus is slower. However, the 70 mA drive capability is
unchanged.
The device stays in READY mode until the output of the
voltage regulator has stabilized and the CS/LWAKE pin
is HIGH (‘1’).
The transmitter may be re-enabled whenever the
FAULT/TXE signal returns high, by removing the inter-
nal fault condition and the CPU returning the FAULT/
TXE high. The transmitter will not be enabled even if
the FAULT/TXE pin is brought high externally, when the
internal fault is still present. However, externally forcing
the FAULT/TXE high while internal fault is still present
should be avoided, since this will induce high current
and power dissipation in the FAULT/TXE pin.
The transmitter is also turned off whenever the voltage
regulator is unstable or recovering from a fault. This
prevents unwanted disruption of the bus during times of
uncertain operation.
1.1.5
POWER-DOWN MODE
1.1.3
OPERATION MODE
If V
REG
is OK (V
REG
>0.8V
REG_NORM
), and the CS/
LWAKE pin, FAULT/TXE pin and TXD pin are HIGH,
the part enters OPERATION mode from either READY
or TRANSMITTER OFF mode.
In this mode, all internal modules are operational. The
internal pull-up resistor between LBUS and VBB is
connected only in this mode.
The device goes into POWER-DOWN mode at the
falling edge on CS/LWAKE; or to the TRANSMITTER
OFF mode at the falling on FAULT/TXE while CS/
LWAKE stays HIGH.
In POWER-DOWN mode, the transceiver and the
voltage regulator are both off. Only the Bus Wake-up
section and the CS/LWAKE pin wake-up circuits are in
operation. This is the lowest power mode.
If any bus activity (e.g. a BREAK character) occurs dur-
ing POWER-DOWN mode, the device will immediately
enter READY mode and enable the voltage regulator.
Then, once the regulator output has stabilized (approx-
imately 0.3 ms to 1.2 ms), it goes to OPERATION
mode. Refer to
Section 1.1.6 “Remote Wake-up”.
The part will also enter READY mode from POWER-
DOWN mode, followed by the OPERATION mode, if
the CS/LWAKE pin becomes active HIGH (‘1’).
1.1.6
REMOTE WAKE-UP
1.1.4
TRANSMITTER OFF MODE
In TRANSMITTER OFF mode, the receiver is enabled
but the L
BUS
transmitter is off. It is a lower power mode.
In order to minimize power consumption, the regulator
operates in a reduced power mode. It has a lower GBW
product and thus is slower. However the 70 mA drive
capability is unchanged.
The remote wake-up sub module observes the L
BUS
in
order to detect bus activity. In POWER DOWN mode,
normal LIN recessive/dominant threshold is disabled,
and the LIN bus Wake-Up Voltage Threshold
V
WK(LBUS)
is used to detect bus activities. Bus activity
is detected when the voltage on the L
BUS
falls below
the LIN bus Wake-Up Voltage Threshold V
WK(LBUS)
(approximately 3.5V) for at least t
BDB
(a typical duration
of 80 µs ) followed by a rising edge. Such a condition
causes the device to leave POWER-DOWN mode.
TABLE 1-1:
State
POR
READY
OPERATION
OVERVIEW OF OPERATIONAL MODES
Transmitter
OFF
OFF
ON
Receiver
OFF
ON
ON
Internal Wake
Module
OFF
OFF
OFF
Voltage
Regulator
OFF
ON
ON
Operation
Transfer to READY mode after V
BB
>V
ON
If CS/LWAKE high, then proceed to
Bus Off state
OPERATION or TRANSMITTER OFF mode.
If CS/LWAKE low level, then Power down
If FAULT/TXE low level, then
TRANSMITTER-OFF mode
On LIN bus rising edge or CS/LWAKE high
level, go to READY mode.
Normal
Operation
mode
Lowest Power
mode
Comments
POWER DOWN
TRANSMITTER-OFF
OFF
OFF
OFF
ON
ON
Activity Detect
OFF
OFF
ON
If CS/LWAKE low level, then Power down
Bus Off state,
If FAULT/TXE high, then OPERATION mode Lower Power
mode
DS22298A-page 4
2012 Microchip Technology Inc.
MCP2021A/2A
1.2
1.2.1
Pin Descriptions
VBB
Please refer to
Table 1-2
for the pinout overview.
If CS/LWAKE =
1,
the device can work in OPERATION
mode (FAULT/TXE =
1)
or TRANSMITTER OFF mode
(FAULT/TXE =
0).
If CS/LWAKE =
0,
the device can work in POWER-
DOWN mode or READY mode.
An internal pull-down resistor will keep the CS/LWAKE
pin low to ensure that no disruptive data will be present
on the bus while the microcontroller is executing a
Power-on Reset and I/O initialization sequence. When
CS/LWAKE is ‘1’, a weak pull-down (~600 kΩ) is used
to reduce current. When CS/LWAKE is ‘0’ a stronger
pull-down (~300 kΩ) is used to maintain the logic level.
This pin may also be used as a local wake-up input
(See
FIGURE 1-9: “Typical Application Circuit”).
The microcontroller will set the I/O pin to control the
CS/LWAKE. An external switch, or other source, can
then wake-up both the transceiver and the
microcontroller.
Note:
CS/LWAKE should NOT be tied directly to
the VREG pin as this could force the
MCP2021A/2A into Operation Mode
before the microcontroller is initialized.
Battery Positive Supply Voltage pin. An external diode
is connected in series to prevent the device from being
reversely powered (refer to
FIGURE 1-9: “Typical
Application Circuit”).
1.2.2
VREG
Positive Supply Voltage Regulator Output pin. An on-
chip LDO gives +5.0 or +3.3V 70 mA regulated voltage
on this pin.
1.2.3
1.2.4
VSS
TXD
Ground pin.
Transmit data input pin (TTL level, HV compliant,
adaptive pull-up). The transmitter reads the data
stream on TXD pin and sends it to LIN bus. The LBUS
pin is low (dominant) when TXD is low, and high
(recessive) when TXD is high.
The Transmit Data Input pin has an internal adaptive
pull-up to an internally-generated 4.2V (approxi-
mately). When TXD is ‘0’, a weak pull-up (~900 kΩ) is
used to reduce current. When TXD is ‘1’, a stronger
pull-up (~300 kΩ) is used to maintain the logic level. A
series reverse-blocking diode allows applying TXD
input voltages greater than the internally generated
4.2V and renders TXD pin HV compliant up to 30V (see
block diagram).
1.2.8
FAULT/TXE
1.2.5
RXD
Fault Detect Output/Transmitter Enable Input pin. The
output section is HV tolerant open drain (up to 30V).
The input section is identical with the TXD section (TTL
level, HV compliant, adaptive pull-up). Internal
adaptive pull-up maintains this input high '1' if the pin is
floating. Its state is defined as shown in
TABLE 1-3:
“FAULT/TXE Truth Table”.
The device is placed in
TRANSMITTER OFF mode whenever this pin is LOW
(‘0’), either from an internal fault condition or by
external drive.
If CS/LWAKE is HIGH (‘1’), the FAULT/TXE signals a
mismatch between the TXD input and the L
BUS
level.
This can be used to detect a bus contention. Since the
bus exhibits a propagation delay, the sampling of the
internal compare is debounced to eliminate false faults.
After the device wakes up, the FAULT/TXE indicates
what wakes the device if CS/LWAKE remains LOW (‘0’)
(refer
Table 1-3).
The FAULT/TXE pin sampled at a rate faster than every
10 µs.
Receive Data Output pin. The RXD pin is a standard
CMOS output pin and it follows the state of the LBUS
pin.
1.2.6
LBUS
LIN Bus pin. LBUS is a bidirectional LIN bus Interface
pin and is controlled by the signal TXD. It has an open
collector output with a current limitation. To reduce
ElectroMagnetic Emission, the slopes during signal
changes are controlled, and the L
BUS
pin has corner-
rounding control for both falling and rising edges.
The internal LIN receiver observes the activities on the
LIN bus, and generates the output signal RXD that
follows the state of the L
BUS
. A 1
st
degree 160 kHz,
low-pass input filter optimizes ElectroMagnetic immu-
nity.
1.2.9
RESET (MCP2022A ONLY)
1.2.7
CS/LWAKE
Chip Select and Local Wake-up Input pin (TTL level,
high voltage tolerant). This pin controls the device state
transition. Refer to
FIGURE 1-1: “State Diagram”.
RESET OUTPUT pin. This pin is open drain with
~90 kΩ pull-up to VREG. It indicates the internal volt-
age has reached a valid, stable level. As long as the
internal voltage is valid (above 0.8 V
REG
), this pin will
remain HIGH (‘1’); otherwise the RESET pin switches
to LOW (‘0’).
2012 Microchip Technology Inc.
DS22298A-page 5
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