SG572288FH8D6UU
March 27, 2008
Ordering Information
Part Numbers
SG572288FH8D6KA
Description
128Mx72 (1GB), DDR3, 240-pin Unbuffered DIMM,
ECC, 128Mx8 Based, DDR3-800-555, 30.00mm, Green
Module (RoHS Compliant).
128Mx72 (1GB), DDR3, 240-pin Unbuffered DIMM,
ECC, 128Mx8 Based, DDR3-800-666, 30.00mm, Green
Module (RoHS Compliant).
128Mx72 (1GB), DDR3, 240-pin Unbuffered DIMM,
ECC, 128Mx8 Based, DDR3-1066-666, 30.00mm,
Green Module (RoHS Compliant).
128Mx72 (1GB), DDR3, 240-pin Unbuffered DIMM,
ECC, 128Mx8 Based, DDR3-1066-777, 30.00mm,
Green Module (RoHS Compliant).
128Mx72 (1GB), DDR3, 240-pin Unbuffered DIMM,
ECC, 128Mx8 Based, DDR3-1066-888, 30.00mm,
Green Module (RoHS Compliant).
128Mx72 (1GB), DDR3, 240-pin Unbuffered DIMM,
ECC, 128Mx8 Based, DDR3-1333-888, 30.00mm,
Green Module (RoHS Compliant).
128Mx72 (1GB), DDR3, 240-pin Unbuffered DIMM,
ECC, 128Mx8 Based, DDR3-1333-999, 30.00mm,
Green Module (RoHS Compliant).
Module Speed
PC3-6400 @ CL 5, 6
SG572288FH8D66B
PC3-6400 @ CL 6
SG572288FH8D6RE
PC3-8500 @ CL 6, 7, 8
SG572288FH8D6LC
PC3-8500 @ CL 7, 8
SG572288FH8D6MD
PC3-8500 @ CL 8
SG572288FH8D6NG
PC3-10600 @ CL 8, 9
SG572288FH8D6PH
PC3-10600 @ CL 9
(All specifications of this module are subject to change without notice.)
Corporate Headquarters:
P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com
Europe:
5 Kelvin Park South, Kelvin South, East Kilbride, G75 ORH, United Kingdom • Tel: +44-870-870-8747 • Fax: +44-870-870-8757
Asia/Pacific:
Plot 18, Lrg Jelawat 4, Kawasan Perindustrian Seberang Jaya 13700, Prai, Penang, Malaysia • Tel: +604-3992909 • Fax: +604-3992903
1
SG572288FH8D6UU
March 27, 2008
Revision History
• March 27, 2008
Datasheet released.
Corporate Headquarters:
P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com
Europe:
5 Kelvin Park South, Kelvin South, East Kilbride, G75 ORH, United Kingdom • Tel: +44-870-870-8747 • Fax: +44-870-870-8757
Asia/Pacific:
Plot 18, Lrg Jelawat 4, Kawasan Perindustrian Seberang Jaya 13700, Prai, Penang, Malaysia • Tel: +604-3992909 • Fax: +604-3992903
2
SG572288FH8D6UU
March 27, 2008
1GByte (128Mx72) DDR3 SDRAM Module - 128Mx8 Based
240-pin DIMM, Unbuffered, ECC
Features
•
•
•
•
•
•
•
Standard = JEDEC
Configuration = ECC
Number of Module Ranks = 1
Number of Devices = 9
V
DD
= V
DDQ
= 1.5V
V
DDSPD
= 1.7V to 3.6V
Cycle Time = 2.5ns (PC3-6400)
1.875 (PC3-8500)
1.5ns (PC3-10600)
CAS Latency = 5, 6, 7, 8, 9, and 10
Additive Latency = 0, CL-1, and CL-2
CAS Write Latency (CWL) = 5, 6, 7, 8
Burst Length = BC4, BL8, BC4 or BL8 (on the fly)
Burst Length = Nibble Sequential & Interleave Mode
Internal Banks per SDRAM = 8
Refresh = 8K/64ms
Device Package = FBGA
Lead Finish = Gold
Length x Height = 133.35mm x 30.00mm
No. of sides = Single-sided
Mating Connector (Examples)
Vertical = AMP - 5-1932000-9
•
•
•
•
•
•
•
•
•
ZQ calibration supported
On chip DLL align DQ, DQS and DQS transition
with CK transition
DM write data-in at both the rising and falling
edges of the data strobe
All addresses and control inputs latched on the
rising edges of the clock
Dynamic On Die Termination supported
Driver strength selected by EMRS
Asynchronous RESET pin supported
Write Levelization supported
8-bit pre-fetch
•
•
•
•
•
•
•
•
•
•
•
•
Addressing
Device Configuration
Number of Internal Banks
Bank Address
Auto precharge
BC switch on the fly
Row Address
Column Address
128Mx8
8
BA0 - BA2
A10/AP
A12/BC
A0 - A13
A0 - A9
Pin Description Table
Symbol
CK0~CK1,
CK0~CK1
CKE0
Type
Polarity
Differential
Crossing
Active High
Function
CK and CK are differential clock inputs. All the DDR3 SDRAM address/control inputs are
sampled on the crossing of the positive edge of CK and the negative edge of CK. Output
(read) data is referenced to the crossing of CK and CK (Both directions of crossing).
Activates the SDRAM CK signal when high and deactivates the CK signal when low. By
deactivating the clocks, CKE low initiates the Power Down mode, or the Self Refresh mode.
Enables the associated SDRAM command decoder when low and disables the command
decoder when high. When decoder is disabled, new commands are ignored but previous
operations continue.This signal provides for external rank selection on systems with multiple
ranks.
When high, termination resistance is enabled for all DQ, DQS, DQS and DM pins, assuming
this function is enabled on the DRAM.
SSTL_15
SSTL_15
CS0
SSTL_15
Active Low
ODT0
SSTL_15
Active High
Corporate Headquarters:
P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com
Europe:
5 Kelvin Park South, Kelvin South, East Kilbride, G75 ORH, United Kingdom • Tel: +44-870-870-8747 • Fax: +44-870-870-8757
Asia/Pacific:
Plot 18, Lrg Jelawat 4, Kawasan Perindustrian Seberang Jaya 13700, Prai, Penang, Malaysia • Tel: +604-3992909 • Fax: +604-3992903
3
SG572288FH8D6UU
March 27, 2008
Pin Description Table
(Contd.)
Symbol
BA0~BA2
Type
SSTL_15
Polarity
-
Function
Selects which SDRAM bank of the eight is activated.
During a Bank Activate command cycle, address inputs define the row address (RA0–
RA13). During a Read or Write command cycle, address inputs define the column address
(CA0–CA9). In addition to the column address, AP is used to invoke auto-precharge opera-
tion at the end of the burst read or write cycle. If AP is high, auto-precharge is selected and
BA0, BA1, BA2 defines the bank to be precharged. If AP is low, auto-precharge is disabled.
During a Precharge command cycle, AP is used in conjunction with BA0, BA1, BA2 to con-
trol which bank(s) to precharge. If AP is high, all banks will be precharged regardless of the
state of BA0, BA1 or BA2. If AP is low, BA0, BA1 and BA2 are used to define which bank to
precharge. A12(BC) is sampled during READ and WRITE commands to determine if burst
chop (on-the-fly) will be performed (HIGH, no burst chop; LOW, burst chopped).
RAS, CAS, and WE (along with CS) define the command being entered.
Data and Check Bit Input/Output pins.
Data strobe for input and output data.
DM is an input mask signal for write data. Input data is masked when DM is sampled high
coincident with that input data during a write access. DM is sampled on both edges of DQS.
Although DM pins are input only, the DM loading matches the DQ and DQS loading.
These signals are tied at the system to either V
SS
or V
DDSPD
to configure the serial SPD
EEPROM address range.
This bidirectional pin is used to transfer data into or out of the SPD EEPROM. An external
resistor may be connected from the SDA bus line to V
DDSPD
to act as a pullup on the sys-
tem board.
This signal is used to clock data into and out of the SPD EEPROM. An external resistor may
be connected from the SCL bus tied to V
DDSPD
to act as a pullup on the system board.
Asynchronous Reset is active when RESET is LOW, and inactive when RESET is HIGH.
RESET must be HIGH during normal operation. RESET is CMOS rail to rail signal with DC
high and low at 80% and 20% of V
DD
.
Power and ground for the DDR3 SDRAM input buffers, and core logic. V
DD
and V
DDQ
pins
are tied to V
DD
/V
DDQ
planes on these modules. V
SS
pins are tied to V
SS
planes on these
modules.
Power supply for the DDR3 SDRAM output buffers to provide improved noise immunity.
V
DDQ
shares the same power plane as V
DD
pins.
Reference voltage for I/O inputs.
-
-
-
-
Reference voltage for address/command inputs.
Power supply for SPD EEPROM. This supply is separate from the V
DD
/V
DDQ
power plane.
EEPROM supply is operable from 1.7V to 3.6V.
Termination voltage for address/command/control/clock nets.
No Connect.
A0~A13
SSTL_15
-
RAS, CAS, WE
DQ0~DQ63
CB0~CB7
DQS0~DQS8
DQS0~DQS8
DM0~DM8
SSTL_15
SSTL_15
SSTL_15
Active Low
-
Differential
Crossing
Active High
SSTL_15
SA0~SA2
-
SDA
-
SCL
-
RESET
CMOS
Active Low
V
DD,
V
SS
Supply
-
V
DDQ
V
REFDQ
V
REFCA
V
DDSPD
V
TT
NC
Supply
Supply
Supply
Supply
Supply
-
-
Corporate Headquarters:
P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com
Europe:
5 Kelvin Park South, Kelvin South, East Kilbride, G75 ORH, United Kingdom • Tel: +44-870-870-8747 • Fax: +44-870-870-8757
Asia/Pacific:
Plot 18, Lrg Jelawat 4, Kawasan Perindustrian Seberang Jaya 13700, Prai, Penang, Malaysia • Tel: +604-3992909 • Fax: +604-3992903
4
SG572288FH8D6UU
March 27, 2008
DDR3 240-pin DIMM Pin List
Pin Pin
No Name
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
REFDQ
V
SS
DQ0
DQ1
V
SS
DQS0
DQS0
V
SS
DQ2
DQ3
V
SS
DQ8
DQ9
V
SS
DQS1
DQS1
V
SS
DQ10
DQ11
V
SS
DQ16
DQ17
V
SS
DQS2
DQS2
V
SS
DQ18
DQ19
V
SS
DQ24
Pin Pin
No Name
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
DQ25
V
SS
DQS3
DQS3
V
SS
DQ26
DQ27
V
SS
CB0
CB1
V
SS
DQS8
DQS8
V
SS
CB2
CB3
V
SS
NC
NC
CKE0
V
DD
BA2
NC
V
DD
A11
A7
V
DD
A5
A4
V
DD
Pin
No
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
Pin
Name
A2
V
DD
CK1
CK1
V
DD
V
DD
V
REFCA
NC
V
DD
A10/AP
BA0
V
DD
WE
CAS
V
DD
CS1 (NC)
Pin
No
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
Pin
Name
DQ41
V
SS
DQS5
DQS5
V
SS
DQ42
DQ43
V
SS
DQ48
DQ49
V
SS
DQS6
DQS6
V
SS
DQ50
DQ51
V
SS
DQ56
DQ57
V
SS
DQS7
DQS7
V
SS
DQ58
DQ59
V
SS
SA0
SCL
SA2
V
TT
Pin
No
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
Pin
Name
V
SS
DQ4
DQ5
V
SS
DM0
NC
V
SS
DQ6
DQ7
V
SS
DQ12
DQ13
V
SS
DM1
NC
V
SS
DQ14
DQ15
V
SS
DQ20
DQ21
V
SS
DM2
NC
V
SS
DQ22
DQ23
V
SS
DQ28
DQ29
Pin
No
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
Pin
Name
V
SS
DM3
NC
V
SS
DQ30
DQ31
V
SS
CB4
CB5
V
SS
DM8
NC
V
SS
CB6
CB7
V
SS
NC
RESET
Pin
No
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
Pin
Name
A1
V
DD
V
DD
CK0
CK0
V
DD
NC
A0
V
DD
BA1
V
DD
RAS
CS0
V
DD
ODT0
A13
V
DD
NC
V
SS
DQ36
DQ37
V
SS
DM4
NC
V
SS
DQ38
DQ39
V
SS
DQ44
DQ45
Pin
No
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
Pin
Name
V
SS
DM5
NC
V
SS
DQ46
DQ47
V
SS
DQ52
DQ53
V
SS
DM6
NC
V
SS
DQ54
DQ55
V
SS
DQ60
DQ61
V
SS
DM7
NC
V
SS
DQ62
DQ63
V
SS
V
DDSPD
SA1
SDA
V
SS
V
TT
ODT1 (NC) 107
V
DD
NC
V
SS
DQ32
DQ33
V
SS
DQS4
DQS4
V
SS
DQ34
DQ35
V
SS
DQ40
108
109
110
111
112
113
114
115
116
117
118
119
120
CKE1 (NC) 199
V
DD
A14 (NC)
A15 (NC)
V
DD
A12/BC
A9
V
DD
A8
A6
V
DD
A3
200
201
202
203
204
205
206
207
208
209
210
Corporate Headquarters:
P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com
Europe:
5 Kelvin Park South, Kelvin South, East Kilbride, G75 ORH, United Kingdom • Tel: +44-870-870-8747 • Fax: +44-870-870-8757
Asia/Pacific:
Plot 18, Lrg Jelawat 4, Kawasan Perindustrian Seberang Jaya 13700, Prai, Penang, Malaysia • Tel: +604-3992909 • Fax: +604-3992903
5
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