EVALUATION KIT AVAILABLE
MAX11335–MAX11340
500ksps, 12-/10-Bit, 4-/8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
General Description
The MAX11335–MAX11340 are 12-/10-bit with external
reference and 500kHz, full-linear-bandwidth, high-speed,
low-power, serial-output successive approximation reg-
ister (SAR) analog-to-digital converters (ADCs). The
MAX11335–MAX11340 provide external access to the
output of the integrated mux and ADC input, to simplify
conditioning. The MAX11335–MAX11340 include both
internal and external clock modes.
These devices feature
scan mode in both internal and external clock modes. The
internal clock mode features internal averaging
to increase
SNR.
The external clock mode features the SampleSetK
technology, a user-programmable analog input channel
sequencer.
The
SampleSet
approach provides greater
sequencing flexibility for multichannel applications while
alleviating significant microcontroller or DSP (controlling
unit) communication overhead.
External pins provide access to the output of the
multiplexer and ADC inputs to simplify multichannel sig-
nal conditioning. The internal clock mode features an inte-
grated FIFO allowing data to be sampled at high speeds
and then held for readout at any time or at a lower clock
rate. Internal averaging is also supported in internal clock
mode improving SNR for noisy input signals. The devices
feature analog input channels that can be configured to
be single-ended inputs, fully differential pairs, or pseudo-
differential inputs with respect to one common input.
The
MAX11335–MAX11340
operate from a 2.35V to 3.6V sup-
ply and consume only 4.2mW at 500ksps.
The MAX11335–MAX11340 include
AutoShutdownK,
fast wake-up, and a high-speed 3-wire serial interface.
The devices feature full power-down mode for optimal
power management.
The
8MHz,
3-wire serial interface
directly connects to SPI, QSPIK, and MICROWIRE
M
devices without external logic.
Excellent dynamic performance, low voltage, low power,
ease of use, and small package size make these convert-
ers ideal for portable battery-powered data-acquisition
applications, and for other applications that demand low
power consumption and small space.
The MAX11335–MAX11340 are available in 32-pin, 5mm
x 5mm, TQFN packages and operate over the -40NC to
+125NC temperature range.
SampleSet and AutoShutdown are trademarks
of Maxim
Integrated Products, Inc.
QSPI is a trademark of Motorola, Inc.
MICROWIRE is a registered trademark of National Semiconductor
Corp.
Benefits and Features
S
Scan Modes, Internal Averaging, and Internal Clock
S
16-Entry First-In/First-Out (FIFO)
S
SampleSet: User-Defined Channel Sequence with
Maximum Length of 256
S
Input Pins
Any
Combination of Single-Ended, Differential
and Pseudo-Differential Pairs Allowed
S
Analog Multiplexer with True Differential
Track/Hold
16-/8-/4-Channel Single-Ended
8-Channel Fully-Differential Pairs
15-/8-/4-Channel Pseudo-Differential Relative to
a Common Input
S
Externally Accessible Multiplex Output and
ADC Input
S
Two Software-Selectable Bipolar Input Ranges
QV
REF+
/2,
QV
REF+
S
Flexible Input Configuration Across All Channels
S
High Accuracy
Q1
LSB INL,
Q1
LSB DNL, No Missing Codes
S
70dB SINAD Guaranteed at 100kHz Input
Frequency
S
1.5V to 3.6V Digital I/O Supply Voltage
S
2.35V to 3.6V Supply Voltage
S
Extended Battery Life for Portable Applications
4.2mW at 500ksps with 3V Supplies
2µA Full-Shutdown Current
S
External Differential Reference (1V to V
DD
)
S
8MHz, 3-Wire SPI-/QSPI-/MICROWIRE-/DSP-
Compatible Serial Interface
S
Wide -40NC to +125NC Operation
S
Space-Saving, 32-Pin, 5mm x 5mm TQFN Packages
S
500ksps Conversion Rate, No Pipeline Delay
Applications
High-Speed Data Acquisition Systems
High-Speed Closed-Loop Systems
Industrial Control Systems
Medical Instrumentation
Battery-Powered Instruments
Portable Systems
For related parts and recommended products to use with this part,
refer to
www.maximintegrated.com/MAX11335-MAX11340.related.
Ordering Information
appears at end of data sheet.
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.
19-6468; Rev 0; 9/12
MAX11335–MAX11340
500ksps, 12-/10-Bit, 4-/8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
ABSOLUTE MAXIMUM RATINGS
V
DD
to GND.............................................................-0.3V to +4V
AOP, AON, AIP, AIN, OVDD, AIN0–AIN13,
CNVST/AIN14,
REF+,
REF-/AIN15 to GND ....................................... -0.3V to the lower of
(V
DD
+ 0.3V) and +4V
CS,
SCLK, DIN, DOUT,
EOC
TO GND .......-0.3V to the lower of
(V
OVDD
+ 0.3V) and +4V
DGND to GND ......................................................-0.3V to +0.3V
Input/Output Current (all pins) ...........................................50mA
Continuous Power Dissipation (T
A
= +70NC)
TQFN (derate 34.4mW/NC above +70NC)..................2758mW
Operating Temperature Range ........................ -40NC to +125NC
Junction Temperature .....................................................+150NC
Storage Temperature Range............................ -65NC to +150NC
Lead Temperature (soldering, 10s) ................................+300NC
Soldering Temperature (reflow) ......................................+260NC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional opera-
tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
PACKAGE THERMAL CHARACTERISTICS (Note 1)
TQFN
Junction-to-Ambient Thermal Resistance (B
JA
)
...........29NC/W
Junction-to-Case Thermal Resistance (B
JC
)...............1.7NC/W
Note 1:
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to
www.maximintegrated.com/thermal-tutorial.
ELECTRICAL CHARACTERISTICS (MAX11335/MAX11336/MAX11337)
(V
DD
= 2.35V to 3.6V, V
OVDD
= 1.5V to 3.6V, f
SAMPLE
= 500ksps, f
SCLK
= 8MHz, 50% duty cycle, V
REF+
= V
DD
, T
A
= -40NC to +125NC,
unless otherwise noted. Typical values are at T
A
= +25NC.) (Note 2)
PARAMETER
DC ACCURACY (Notes 3 and 4)
Resolution
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Gain Error
Offset Error Temperature Coefficient
Gain Temperature Coefficient
Channel-to-Channel Offset Matching
Line Rejection
Signal-to-Noise Plus Distortion
Signal-to-Noise Ratio
Total Harmonic Distortion
(Up to the 5th Harmonic)
Spurious-Free Dynamic Range
Intermodulation Distortion
Full-Power Bandwidth
Full-Linear Bandwidth
PSR
SINAD
SNR
THD
SFDR
IMD
f
1
= 99.2432kHz, f
2
= 69.2139kHz
-3dB
-0.1dB
SINAD ≥ 70dB
77
(Note 6)
70
70
DYNAMIC PERFORMANCE (100kHz, Input Sine Wave) (Notes 3 and 7)
71.9
72.3
-83
84
-85
30
5
0.5
-76
dB
dB
dB
dB
dB
MHz
MHz
OE
TC
GE
TC
(Note 5)
RES
INL
DNL
No missing codes
1.2
-0.02
Q2
Q0.8
Q0.5
Q0.3
Q2
12 bit
12
Q1.0
Q1.0
Q3.0
Q5.5
Bits
LSB
LSB
LSB
LSB
ppm/NC
ppm/NC
LSB
LSB/V
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Maxim Integrated
2
MAX11335–MAX11340
500ksps, 12-/10-Bit, 4-/8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
ELECTRICAL CHARACTERISTICS (MAX11335/MAX11336/MAX11337) (continued)
(V
DD
= 2.35V to 3.6V, V
OVDD
= 1.5V to 3.6V, f
SAMPLE
= 500ksps, f
SCLK
= 8MHz, 50% duty cycle, V
REF+
= V
DD
, T
A
= -40NC to +125NC,
unless otherwise noted. Typical values are at T
A
= +25NC.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
-0.5dB below full-scale of 99.2432kHz
sine wave input to the channel being
sampled, apply full-scale 69.2139kHz
sine wave signal to all 15 nonselected
input channels.
t
PU
t
ACQ
Internally clocked (Note 8)
Conversion Time
External Clock Frequency
Aperture Delay
Aperture Jitter
ANALOG INPUT
Unipolar, (single ended and pseudo-
differential)
Bipolar
(Note 9)
Range bit set to 0
Range bit set to 1
0
-V
REF+
/2
-V
REF+
-0.1
-0.1
15
pF
7.5
V
REF+
V
REF+
/2
V
REF+
V
REF+
+ 0.1
Q1.5
V
FA
V
RMS
t
CONV
f
SCLK
Externally clocked, f
SCLK
= 8MHz,
16 cycles (Note 8)
2000
0.16
8
30
8
Conversion cycle, external clock
312
5.9
MIN
TYP
MAX
UNITS
Crosstalk
-88
dB
CONVERSION RATE
Power-Up Time
Acquisition Time
2
Cycles
ns
µs
ns
MHz
ns
ps
Input Voltage Range
V
INA
Absolute Input Voltage Range
Static Input Leakage Current
I
ILA
AIN+, AIN- relative to GND
V
AIN
= V
DD
, GND
During acquisition time;
RANGE bit = 0 (Note 10)
During acquisition time;
RANGE bit = 1 (Note 10)
Input Capacitance
C
AIN
EXTERNAL REFERENCE INPUT
REF- Input Voltage Range
REF+ Input Voltage Range
REF+ Input Current
V
REF-
V
REF+
I
REF+
V
REF+
= 2.5V, f
SAMPLE
= 500ksps
V
REF+
= 2.5V, f
SAMPLE
= 0Msps
-0.3
1
36.7
0.1
V
OVDD
O
0.25
V
OVDD
O
0.75
V
OVDD
O
0.15
+1
V
DD
+ 50mV
V
V
FA
DIGITAL INPUTS (SCLK, DIN,
CS, CNVST)
Input Voltage Low
Input Voltage High
Input Hysteresis
V
IL
V
IH
V
HYST
V
V
mV
Maxim Integrated
3
MAX11335–MAX11340
500ksps, 12-/10-Bit, 4-/8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
ELECTRICAL CHARACTERISTICS (MAX11335/MAX11336/MAX11337) (continued)
(V
DD
= 2.35V to 3.6V, V
OVDD
= 1.5V to 3.6V, f
SAMPLE
= 500ksps, f
SCLK
= 8MHz, 50% duty cycle, V
REF+
= V
DD
, T
A
= -40NC to +125NC,
unless otherwise noted. Typical values are at T
A
= +25NC.) (Note 2)
PARAMETER
Input Leakage Current
Input Capacitance
DIGITAL OUTPUTS (DOUT,
EOC)
Output Voltage Low
Output Voltage High
Three-State Leakage Current
Three-State Output Capacitance
POWER REQUIREMENTS
Positive Supply Voltage
Digital I/O Supply Voltage
Positive Supply Current
V
DD
V
OVDD
f
SAMPLE
= 500ksps
I
DD
f
SAMPLE
= 0Msps (500ksps devices)
Full shutdown
Normal mode
(External
Reference)
Power Dissipation
AutoStandby
V
DD
= 3V,
f
SAMPLE
= 500ksps
V
DD
= 2.35V,
f
SAMPLE
= 500ksps
V
DD
= 3V,
f
SAMPLE
= 500ksps
V
DD
= 2.35V,
f
SAMPLE
= 500ksps
V
DD
= 3V
V
DD
= 2.35V
125
40
C
LOAD
=
10pF
V
OVDD
= 1.5V to 2.35V
V
OVDD
= 2.35V to 3.6V
4
4
60
16.5
15
15
16
14
4
1
2.35
1.5
3.0
3.0
1.4
1
0.0015
4.2
3.1
mW
1.5
0.9
4.5
2.1
FW
0.006
3.6
3.6
2
mA
V
V
V
OL
V
OH
I
L
C
OUT
I
SINK
= 200FA
I
SOURCE
= 200FA
CS
= V
DD
CS
= V
DD
V
OVDD
O
0.85
-0.3
4
Q1.5
V
OVDD
O
0.15
V
V
FA
pF
SYMBOL
I
IN
C
IN
CONDITIONS
V
AIN
= 0V or V
DD
MIN
TYP
Q0.09
3
MAX
Q1.0
UNITS
FA
pF
Full/
AutoShutdown
TIMING CHARACTERISTICS (Figure 1) (Note 11)
SCLK Clock Period
SCLK Duty Cycle
SCLK Fall to DOUT Transition
16th SCLK Fall to DOUT Disable
14th SCLK Fall to DOUT Disable
SCLK Fall to DOUT Enable
DIN to SCLK Rise Setup
SCLK Rise to DIN Hold
t
DOE
t
DS
t
DH
t
CP
t
CH
t
DOT
t
DOD
Externally clocked conversion
ns
%
ns
ns
ns
ns
ns
ns
C
LOAD
= 10pF, channel ID on
C
LOAD
= 10pF, channel ID off
C
LOAD
= 10pF
Maxim Integrated
4
MAX11335–MAX11340
500ksps, 12-/10-Bit, 4-/8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
ELECTRICAL CHARACTERISTICS (MAX11335/MAX11336/MAX11337) (continued)
(V
DD
= 2.35V to 3.6V, V
OVDD
= 1.5V to 3.6V, f
SAMPLE
= 500ksps, f
SCLK
= 8MHz, 50% duty cycle, V
REF+
= V
DD
, T
A
= -40NC to +125NC,
unless otherwise noted. Typical values are at T
A
= +25NC.) (Note 2)
PARAMETER
CS
Fall to SCLK Fall Setup
SCLK Fall to
CS
Fall Hold
CNVST
Pulse Width
CS
or
CNVST
Rise to
EOC
Low
(Note 6)
CS
Pulse Width
SYMBOL
t
CSS
t
CSH
t
CSW
t
CNV_INT
t
CSBW
See Figure 6
See Figure 7, f
SAMPLE
= 500ksps
5
CONDITIONS
MIN
4
1
5
5.3
6.2
TYP
MAX
UNITS
ns
ns
ns
Fs
ns
ELECTRICAL CHARACTERISTICS (MAX11338/MAX11339/MAX11340)
(V
DD
= 2.35V to 3.6V, V
OVDD
= 1.5V to 3.6V, f
SAMPLE
= 500ksps, f
SCLK
= 8MHz, 50% duty cycle, V
REF+
= V
DD
, T
A
= -40NC to +125NC,
unless otherwise noted. Typical values are at T
A
= +25NC.) (Note 2)
PARAMETER
DC ACCURACY (Notes 3 and 4)
Resolution
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Gain Error
Offset Error Temperature
Coefficient
Gain Temperature Coefficient
Channel-to-Channel Offset
Matching
Line Rejection
Signal-to-Noise Plus Distortion
Signal-to-Noise Ratio
Total Harmonic Distortion
(Up to the 5th Harmonic)
Spurious-Free Dynamic Range
Intermodulation Distortion
Full-Power Bandwidth
Full-Linear Bandwidth
PSR
SINAD
SNR
THD
SFDR
IMD
f
1
= 99.2432kHz, f
2
= 69.2139kHz
-3dB
-0.1dB
SINAD ≥ 61dB
76
(Note 6)
61
61
DYNAMIC PERFORMANCE (100kHz, Input Sine Wave) (Notes 3 and 7)
61.5
61.5
-82.5
83.4
-83
30
5
0.5
-75
dB
dB
dB
dB
dB
MHz
MHz
MHz
OE
TC
GE
TC
(Note 5)
RES
INL
DNL
No missing codes
0.7
0
±2
±0.8
±0.5
0.2
±1.0
10 bit
10
±0.4
±0.4
±1.2
±1.5
Bits
LSB
LSB
LSB
LSB
ppm/NC
ppm/NC
LSB
LSB/V
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Maxim Integrated
5
模拟电子
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
