19-3446; Rev 3; 1/07
KIT
ATION
EVALU
E
BL
AVAILA
12-Bit, 200Msps, High-Dynamic-Performance,
Dual DAC with CMOS Inputs
General Description
The MAX5873 is an advanced 12-bit, 200Msps, dual
digital-to-analog converter (DAC). This DAC meets the
demanding performance requirements of signal synthesis
applications found in wireless base stations and other
communications applications. Operating from 3.3V and
1.8V supplies, this dual DAC offers exceptional dynamic
performance such as 78dBc spurious-free dynamic range
(SFDR) at f
OUT
= 16MHz and supports update rates of
200Msps, with a power dissipation of only 255mW.
The MAX5873 utilizes a current-steering architecture
that supports a 2mA to 20mA full-scale output current
range, and allows a 0.1V
P-P
to 1V
P-P
differential output
voltage swing. The MAX5873 features an integrated
1.2V bandgap reference and control amplifier to ensure
high-accuracy and low-noise performance. A separate
reference input (REFIO) allows for the use of an exter-
nal reference source for optimum flexibility and
improved gain accuracy.
The digital and clock inputs of the MAX5873 accept
3.3V CMOS voltage levels. The MAX5873 features a
flexible input data bus that allows for dual-port input or
a single-interleaved data port. The MAX5873 is avail-
able in a 68-pin QFN package with an exposed paddle
(EP) and is specified for the extended temperature
range (-40°C to +85°C).
Refer to the MAX5874 and MAX5875 data sheets for
pin-compatible 14-bit and 16-bit versions of the
MAX5873, respectively. Refer to the MAX5876 for an
LVDS-compatible version of the MAX5873.
Features
♦
200Msps Output Update Rate
♦
Noise Spectral Density = -152dBFS/Hz
at f
OUT
= 16MHz
♦
Excellent SFDR and IMD Performance
SFDR = 78dBc at f
OUT
= 16MHz (to Nyquist)
SFDR = 73dBc at f
OUT
= 80MHz (to Nyquist)
IMD = -85dBc at f
OUT
= 10MHz
IMD = -74dBc at f
OUT
= 80MHz
♦
ACLR = 74dB at f
OUT
= 61MHz
♦
2mA to 20mA Full-Scale Output Current
♦
CMOS-Compatible Digital and Clock Inputs
♦
On-Chip 1.2V Bandgap Reference
♦
Low 255mW Power Dissipation
♦
68-Lead QFN-EP Package
♦
Evaluation Kit Available (MAX5873EVKIT)
MAX5873
Ordering Information
PART
MAX5873EGK-D
MAX5873EGK+D
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
PIN-
PACKAGE
68 QFN-EP*
68 QFN-EP*
PKG
CODE
G6800-4
G6800-4
*EP
= Exposed pad.
+
Denotes lead-free package.
D
= Dry pack.
Pin Configuration
TOP VIEW
DV
DD1.8
N.C.
N.C.
N.C.
N.C.
A10
A11
A5
A6
A7
A8
A9
B0
B1
B2
B3
B4
Applications
Base Stations: Single-Carrier UMTS, CDMA, GSM
Communications: Fixed Broadband Wireless
Access, Point-to-Point Microwave
Direct Digital Synthesis (DDS)
Cable Modem Termination System (CMTS)
Automated Test Equipment (ATE)
Instrumentation
A4
A3
A2
A1
A0
N.C.
N.C.
N.C.
N.C.
GND
DV
DD3.3
GND
GND
AV
DD3.3
GND
REFIO
FSADJ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
68
67 66 65 64
63 62 61 60 59 58
57 56 55 54 53 52
51
50
49
48
47
46
45
44
B5
B6
B7
B8
B9
B10
B11
SELIQ
GND
XOR
DORI
PD
TORB
CLKP
CLKN
GND
AV
CLK
Selector Guide
PART
MAX5873
MAX5874
MAX5875
MAX5876
MAX5877
MAX5878
RESOLUTION
(BITS)
12
14
16
12
14
16
UPDATE
RATE (Msps)
200
200
200
250
250
250
LOGIC
INPUTS
CMOS
CMOS
CMOS
LVDS
LVDS
LVDS
MAX5873
43
42
41
40
39
38
37
36
35
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
AV
DD1.8
GND
OUTQN
OUTQP
GND
GND
OUTIN
DACREF
OUTIP
GND
AV
DD3.3
AV
DD3.3
GND
AV
DD3.3
AV
DD3.3
GND
QFN
________________________________________________________________
Maxim Integrated Products
AV
DD1.8
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
12-Bit, 200Msps, High-Dynamic-Performance,
Dual DAC with CMOS Inputs
MAX5873
ABSOLUTE MAXIMUM RATINGS
AV
DD1.8
, DV
DD1.8
to GND, DACREF ................. -0.3V to +2.16V
AV
DD3.3
, DV
DD3.3
, AV
CLK
to GND, DACREF ....... -0.3V to +3.9V
REFIO, FSADJ to GND, DACREF ........-0.3V to (AV
DD3.3
+ 0.3V)
OUTIP, OUTIN, OUTQP, OUTQN
to GND, DACREF .................................-1V to (AV
DD3.3
+ 0.3V)
CLKP, CLKN to GND, DACREF..............-0.3V to (AV
CLK
+ 0.3V)
A11/B11–A0/B0, XOR, SELIQ to
GND, DACREF ...................................-0.3V to (DV
DD3.3
+ 0.3V)
TORB,
DORI,
PD to GND, DACREF........-0.3V to (DV
DD3.3
+ 0.3
Continuous Power Dissipation (T
A
= +70°C)
68-Pin QFN-EP
(derate 41.7mW/°C above +70°C) (Note 1) ...........3333.3mW
Thermal Resistance
θ
JA
(Note 1)...................................+24°C/W
Operating Temperature Range ......................... -40°C to +85°C
Junction Temperature .................................................... +150°C
Storage Temperature Range ........................... -60°C to +150°C
Lead Temperature (soldering, 10s) ............................... +300°C
Note 1:
Themal resistors based on a multilayer board with 4 x 4 via array in exposed paddle area.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AV
DD3.3
= DV
DD3.3
= AV
CLK
= 3.3V, AV
DD1.8
= DV
DD1.8
= 1.8V, GND = 0, f
CLK
= f
DAC
, external reference V
REFIO
= 1.25V, output load
50Ω double terminated, transformer-coupled output, I
OUTFS
= 20mA, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.) (Note 2)
PARAMETER
STATIC PERFORMANCE
Resolution
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Offset-Drift Tempco
Full-Scale Gain Error
Gain-Drift Tempco
Full-Scale Output Current
Output Compliance
Output Resistance
Output Capacitance
DYNAMIC PERFORMANCE
Clock Frequency
Output Update Rate
Noise Spectral Density
f
CLK
f
DAC
f
DAC
= f
CLK
/ 2, single-port mode
f
DAC
= f
CLK
, dual-port mode
f
DAC
= 150MHz
f
DAC
= 200MHz
f
OUT
= 16MHz, -12dBFS
f
OUT
= 80MHz, -12dBFS
1
1
1
-152
-153
200
100
200
MHz
Msps
dBFS/
Hz
R
OUT
C
OUT
I
OUT
GE
FS
External reference
Internal reference
External reference
(Note 3)
Single-ended
2
-0.5
1
5
INL
DNL
OS
Measured differentially
Measured differentially
-0.025
12
±0.2
±0.13
±0.001
±10
±1
±100
±50
20
+1.1
+0.025
Bits
LSB
LSB
%FS
ppm/°C
%FS
ppm/°C
mA
V
MΩ
pF
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
2
_______________________________________________________________________________________
12-Bit, 200Msps, High-Dynamic-Performance,
Dual DAC with CMOS Inputs
ELECTRICAL CHARACTERISTICS (continued)
(AV
DD3.3
= DV
DD3.3
= AV
CLK
= 3.3V, AV
DD1.8
= DV
DD1.8
= 1.8V, GND = 0, f
CLK
= f
DAC
, external reference V
REFIO
= 1.25V, output load
50Ω double terminated, transformer-coupled output, I
OUTFS
= 20mA, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
f
OUT
= 1MHz, 0dBFS
f
OUT
= 1MHz, -6dBFS
f
DAC
= 100MHz
f
OUT
= 1MHz, -12dBFS
f
OUT
= 10MHz, -12dBFS
Spurious-Free Dynamic Range
to Nyquist
f
OUT
= 30MHz, -12dBFS
SFDR
f
OUT
= 10MHz, -12dBFS
f
OUT
= 16MHz, -12dBFS,
T
A
≥
+25
o
C
f
OUT
= 16MHz, -12dBFS
f
OUT
= 50MHz, -12dBFS
f
OUT
= 80MHz, -12dBFS
Spurious-Free Dynamic Range,
25MHz Bandwidth
SFDR
f
DAC
= 150MHz
f
DAC
= 100MHz
Two-Tone IMD
TTIMD
f
DAC
= 200MHz
Four-Tone IMD, 1MHz
Frequency Spacing, GSM Model
Adjacent Channel Leakage Power
Ratio 3.84MHz Bandwidth,
W-CDMA Model
Output Bandwidth
INTER-DAC CHARACTERISTICS
Gain Matching
Gain-Matching Tempco
Phase Matching
Phase-Matching Tempco
Channel-to-Channel Crosstalk
REFERENCE
Internal Reference Voltage Range
Reference Input Compliance
Range
Reference Input Resistance
Reference Voltage Drift
V
REFIO
V
REFIOCR
R
REFIO
TCO
REF
1.14
0.125
10
±25
1.2
1.26
1.250
V
V
kΩ
ppm/°C
∆Gain
∆Gain/°C
∆Phase
∆Phase/°C
f
CLK
= 200MHz, f
OUT
= 50MHz, 0dBFS
f
OUT
= 60MHz
f
OUT
= DC - 80MHz
f
OUT
= DC
±0.2
+0.01
±20
±0.25
±0.002
-70
dB
ppm/°C
Degrees
Degrees/
°C
dB
FTIMD
f
DAC
= 150MHz
f
DAC
=
184.32MHz
(Note 4)
f
OUT
= 16MHz, -12dBFS
f
OUT1
= 9MHz, -7dBFS;
f
OUT2
= 10MHz, -7dBFS
f
OUT1
= 79MHz, -7dBFS;
f
OUT2
= 80MHz, -7dBFS
f
OUT
= 16MHz, -12dBFS
72
68
MIN
TYP
86
82
80
85
80
80
78
78
77
73
85
-85
dBc
-74
-82
dBc
dBc
dBc
MAX
UNITS
MAX5873
f
DAC
= 200MHz
ACLR
BW
-1dB
f
OUT
= 61.44MHz
74
240
dB
MHz
_______________________________________________________________________________________
3
12-Bit, 200Msps, High-Dynamic-Performance,
Dual DAC with CMOS Inputs
MAX5873
ELECTRICAL CHARACTERISTICS (continued)
(AV
DD3.3
= DV
DD3.3
= AV
CLK
= 3.3V, AV
DD1.8
= DV
DD1.8
= 1.8V, GND = 0, f
CLK
= f
DAC
, external reference V
REFIO
= 1.25V, output load
50Ω double terminated, transformer-coupled output, I
OUTFS
= 20mA, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.) (Note 2)
PARAMETER
Output Fall Time
Output Rise Time
Output-Voltage Settling Time
Output Propagation Delay
Glitch Impulse
Output Noise
TIMING CHARACTERISTICS
Data to Clock Setup Time
Data to Clock Hold Time
Single-Port (Interleaved Mode)
Data Latency
Dual-Port (Parallel Mode) Data
Latency
Minimum Clock Pulse-Width High
Minimum Clock Pulse-Width Low
t
CH
t
CL
CLKP, CLKN
CLKP, CLKN
0.7 x
DV
DD3.3
0.3 x
DV
DD3.3
1
V
PD
= V
TORB
= V
DORI
= 3.3V
C
IN
Sine wave
Square wave
SR
CLK
V
COM
R
CLK
C
CLK
AV
DD3.3
AV
DD1.8
3.135
1.710
(Note 7)
1.5
2.5
> 1.5
> 0.5
> 100
AV
CLK
/ 2
±0.3
5
2.5
3.3
1.8
3.465
1.890
20
t
SETUP
t
HOLD
Referenced to rising edge of clock (Note 6)
Referenced to rising edge of clock (Note 6)
Latency to I output
Latency to Q output
-0.6
2.1
-1.2
1.5
9
8
5.5
2.4
2.4
ns
ns
Clock
cycles
Clock
cycles
ns
ns
N
OUT
SYMBOL
t
FALL
t
RISE
t
SETTLE
t
PD
CONDITIONS
90% to 10% (Note 5)
10 % to 90% (Note 5)
Output settles to 0.025% FS (Note 5)
Excluding data latency (Note 5)
Measured differentially
I
OUTFS
= 2mA
I
OUTFS
= 20mA
MIN
TYP
0.7
0.7
14
1.1
1
30
30
MAX
UNITS
ns
ns
ns
ns
pV
•
s
pA/√Hz
ANALOG OUTPUT TIMING (See Figure 4)
CMOS LOGIC INPUTS (A11/B11–A0/B0, XOR, SELIQ, PD, TORB,
DORI)
Input Logic High
Input Logic Low
Input Leakage Current
PD, TORB,
DORI
Internal
Pulldown Resistance
Input Capacitance
CLOCK INPUTS (CLKP, CLKN)
Differential Input
Voltage Swing
Differential Input Slew Rate
External Common-Mode Voltage
Range
Input Resistance
Input Capacitance
POWER SUPPLIES
Analog Supply Voltage Range
V
V
P-P
V/µs
V
kΩ
pF
V
IH
V
IL
I
IN
V
V
µA
MΩ
pF
4
_______________________________________________________________________________________
12-Bit, 200Msps, High-Dynamic-Performance,
Dual DAC with CMOS Inputs
ELECTRICAL CHARACTERISTICS (continued)
(AV
DD3.3
= DV
DD3.3
= AV
CLK
= 3.3V, AV
DD1.8
= DV
DD1.8
= 1.8V, GND = 0, f
CLK
= f
DAC
, external reference V
REFIO
= 1.25V, output load
50Ω double terminated, transformer-coupled output, I
OUTFS
= 20mA, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.) (Note 2)
PARAMETER
Digital Supply Voltage Range
Clock Supply Voltage Range
Analog Supply
Current
SYMBOL
DV
DD3.3
DV
DD1.8
AV
CLK
I
AVDD3.3
+ I
AVCLK
I
AVDD1.8
I
DVDD3.3
I
DVDD1.8
Power Dissipation
Power-Supply
Rejection Ratio
P
DISS
PSRR
f
DAC
= 200Msps, f
OUT
= 1MHz
Power-down
f
DAC
= 200Msps, f
OUT
= 1MHz
Power-down
f
DAC
= 200Msps, f
OUT
= 1MHz
Power-down
f
DAC
= 200Msps, f
OUT
= 1MHz
Power-down
f
DAC
= 200Msps, f
OUT
= 1MHz
Power-down
AV
DD3.3
= AV
CLK
= DV
DD3.3
= +3.3V
±5%
(Notes 7, 8)
-0.1
CONDITIONS
MIN
3.135
1.710
3.135
TYP
3.3
1.8
3.3
52
0.001
24
0.001
0.5
0.001
20
0.001
255
14
+0.1
300
25
3
32
MAX
3.465
1.890
3.465
58
UNITS
V
V
mA
mA
mA
mA
mW
µW
%FS/V
MAX5873
Digital Supply
Current
Note 2:
Specifications at T
A
≥
+25°C are guaranteed by production testing. Specifications at T
A
< +25°C are guaranteed by design
and characterization data.
Note 3:
Nominal full-scale current I
OUTFS
= 32 x I
REF
.
Note 4:
This parameter does not include update-rate-dependent effects of sin(x)/x filtering inherent in the MAX5873.
Note 5:
Parameter measured single-ended into a 50Ω termination resistor.
Note 6:
Not production tested. Guaranteed by design and characterization data.
Note 7:
A differential clock input slew rate of > 100V/µs is required to achieve the specified dynamic performance.
Note 8:
Parameter defined as the change in midscale output caused by a ±5% variation in the nominal supply voltage.
Typical Operating Characteristics
(AV
DD3.3
= DV
DD3.3
= AV
CLK
= 3.3V, AV
DD1.8
= DV
DD1.8
= 1.8V, external reference, V
REFIO
= 1.25V, R
L
= 50Ω double-terminated,
I
OUTFS
= 20mA, T
A
= +25°C, unless otherwise noted.)
SINGLE-TONE SFDR vs. OUTPUT
FREQUENCY (f
CLK
= 50Msps)
MAX5873 toc01
SINGLE-TONE SFDR vs. OUTPUT
FREQUENCY (f
CLK
= 100Msps)
MAX5873 toc02
SINGLE-TONE SFDR vs. OUTPUT
FREQUENCY (f
CLK
= 150Msps)
0dBFS
80
-12dBFS
60
-6dBFS
MAX5873 toc03
100
0dBFS
80
-12dBFS
SFDR (dBc)
60
-6dBFS
100
0dBFS
80
-12dBFS
SFDR (dBc)
60
-6dBFS
100
40
40
SFDR (dBc)
50
40
20
20
20
0
0
5
10
15
20
25
f
OUT
(MHz)
0
0
10
20
30
40
f
OUT
(MHz)
0
0
15
30
45
60
75
f
OUT
(MHz)
_______________________________________________________________________________________
5
实时操作系统RTOS
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
