Advanced Power
Electronics Corp.
FEATURES
Ideal for DDR-I, DDR-II and DDR-III V
TT
Applications
Sink and Source up to 2.5Amp
Integrated Power MOSFETs
Generates Termination Voltage for SSTL_2, SSTL_18,
HSTL, SCSI-2 and SCSI-3 Interfaces.
High Accuracy Output Voltage at Full-Load
Output Adjustment by Two External Resistors
Built-in Soft-start Function
Shutdown for Suspend to RAM (STR) Functionality
with High-Impedance Output
Current Limiting Protection
On-Chip Thermal Protection
Available in ESOP-8 Packages
V
IN
and V
CNTL
Under Voltage Protection
RoHS Compliant and Halogen Free Product
AP1270AMP
DESCRIPTIOON
The AP1270AMP is a simple, cost-effective and
high-speed linear regulator designed to generate
termination voltage in double data rate (DDR) memory
system to comply with the JEDEC SSTL_2 and
SSTL_18 or other specific interfaces such as HSTL,
SCSI-2 and SCSI-3 etc. devices requirements. The
regulator is capable of actively sinking or sourcing up to
2.5A while regulating an output voltage to within 40mV.
The output termination voltage cab be tightly regulated
to track 1/2V
DDQ
by two external voltage divider resistors
or the desired output voltage can be pro-grammed by
externally forcing the REFEN pin voltage.
The AP1270AMP also incorporates a high-speed
differential amplifier to provide ultra-fast response in
line/load transient. Other features include extremely low
initial offset voltage, excellent load regulation, current
limiting in bi-directions and on-chip thermal shut-down
protection.Built-in
softstart
function
avoids
a
misoperation by inrush current.
The AP1270AMP are available in the ESOP-8
surface mount packages.
2.5A SINK/SOURCE BUS TERMINATION REGULATOR
APPLICATION
Desktop PCs, Notebooks, and Workstations
Graphics Card Memory Termination
Set Top Boxes, Digital TVs, Printers
Embedded Systems
Active Termination Buses
DDR-I, DDR-II and DDR-III Memory Systems
TYPICAL APPLICATION
VIN
VCNTL
VIN
CIN
R1
VCNTL
CCNTL
AP1270AMP
RTT
VOUT
REFEN
Shutdown
R2
CSS
VOUT
COUT
RDUMMY
GND
Enable
R1 = R2 = 100 KΩ , RTT = 50Ω / 33Ω / 25Ω
COUT = 10uF ( + 100 uF under the worst case testing condition )
CSS = 1uF , CIN = 470 uF (Low ESR) , CCNTL = 47uF
Data and specifications subject to change without notice
1
20130617V3.1
Advanced Power
Electronics Corp.
ABSOLUTE MAXIMUM RATINGS
(Note1)
Input Voltage (V
IN
) ------------------------------------------ 6V
CNTL Pin Voltage (V
CNTL
) -------------------------------- 6V
Power Dissipation (P
D
) ------------------------------------ Internally Limited
Storage Temperature Range (T
ST
) --------------------- -65 to +150°C
Lead Temperature (Soldering, 10sec.) ---------------
Thermal Resistance from Junction to Case (R
thjc
)
260°C
28°C/W
AP1270AMP
Note1 : Exceeding the absolute maximum rating may damage the device.
OPERATING RATING
(Note2)
Input Voltage (V
IN
) ------------------------------------------ 2.5V to 1.5V +3%
CNTL Pin Voltage (V
CNTL
) -------------------------------- 5.5V or 3.3V +5%
Junction Temperature Range (T
J
) ---------------------
Ambient Temperature Range (T
A
) ---------------------
-40 to +125°C
-40 to +85°C
Note2 : The device is not guaranteed to function outside its operating conditions.
ORDERING / PACKAGE INFORMATION
( Top View )
AP1270 AX
VIN
GND
REFEN
1
2
3
4
ESOP-8
8
NC
GND
7 NC
6
5
VCNTL
NC
Package Type
MP : ESOP-8
VOUT
R
thja
= 75
o
C/W
ELECTRICAL SPECIFICATIONS
(V
IN
=1.8V, V
CNTL
=3.3V, V
REFEN
=0.9V, C
OUT
=10uF(Ceramic), T
A
=25
o
C, unless otherwise specified)
Parameter
Input
VCNTL Operation Current
Standby Current
VIN Shutdown Current
UVP Function
VCNTL UVP Rising Threshold
VCNTL UVP Hysteresis
VIN UVP Rising Threshold
VIN UVP Hysteresis
Output (DDR / DDRII / DDRIII)
Output Offset Voltage
(Note3)
Load Regulation
(Note4)
SYM
I
CNTL
I
STBY
I
VIN
V
COP
V
CHYS
V
IOP
V
IHYS
TEST CONDITION
I
OUT
= 0A
V
REFEN=
0V (Shutdown)
V
REFEN=
0V (Shutdown)
V
CNTL
Rising
V
IOP
Rising
MIN
-
-
-
2.4
-
0.8
-
TYP
1
2
-
2.55
0.35
0.95
0.15
-
-
-
-
MAX
2.5
5
5
2.7
-
1.1
-
20
20
20
20
UNITS
mA
uA
uA
V
V
V
V
ΔV
OS
ΔV
Load
I
OUT
= 10mA
I
OUT
= -10mA
I
OUT
=10mA ~ 2.5A
I
OUT
=-10mA ~ -2.5A
-20
-20
-20
-20
mV
2
Advanced Power
Electronics Corp.
ELECTRICAL SPECIFICATIONS (Cont.)
Parameter
Protection
Current Limit
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
ENABLE and Soft-Start
REFEN Threshold
Soft-Start Interval
V
EN
T
SS
∆V
OUT
=1V
0.15
-
I
LIM
T
SD
ΔT
SD
3.3V < V
CNTL
< 5V
3.3V < V
CNTL
< 5V
2.6
-
-
SYM
TEST CONDITION
MIN
AP1270AMP
TYP
-
150
20
-
0.8
MAX
-
-
-
0.4
-
UNITS
A
o
C
V
ms
Note3. V
OS
offset is the voltage measurement defined as V
OUT
subtracted from V
REFEN
.
Note4. Regulation is measured at constant junction temperature by using a 1ms(on) / 9ms(off) current pulse. Devices are tested for load regulation
in the load range from 10mA to 2.5A peak for source and -10mA to -2.5A peak for sink capability.
PIN DESCRIPTIONS
PIN SYMBOL
VIN
GND
VOUT
VCNTL
REFEN
PIN DESCRIPTION
Power Input Voltage.
Ground Pin
Output Voltage
Gate Drive Voltage
Reference Voltage Input and Chip Enable
BLOCK DIAGRAM
VCNTL
UVP
Function
VIN
OTP
Function
REFEN
Soft-Start
Function
ENABLE
FUNCTION
OCP
Function
GATE
CONTROL
LOGIC
ERROR
AMPLIFIER
VOUT
GND
3
Advanced Power
Electronics Corp.
APPLICATION INFORMATION
Input Capacitor and Layout Consideration
AP1270AMP
Place the input bypass capacitor as close as possible to the AP1270AMP. A low ESR
capacitor larger than 470uF is recommended for the input capacitor. Use short and wide traces to
minimize parasitic resistance and inductance.
Inappropriate layout may result in large parasitic inductance and cause undesired oscillation
between AP1270AMP and the preceding powe converter.
Consideration while designs the resistance of voltage divider
Make sure the sinking current capability of pull-down NMOS if the lower resistance was
chosen so that the voltage on V
REFEN
is below 0.15V. In addition, the capacitor and voltage divider
form the lowpass filter. There are two reasons doing this design; one is for output voltage soft-
start while another is for noise immunity.
Thermal Consideration
AP1270AMP regulators have internal thermal limiting circuitry designed to protect the device
during overload conditions.For continued operation, do not exceed maximum operation junction
temperature 125
o
C. The power dissipation definition in device is:
P
D
= (V
IN
- V
OUT
) x I
OUT
+ V
IN
x I
Q
The maximum power dissipation depends on the thermal resistance of IC package, PCB
layout, the rate of surroundings airflow and temperature difference between junction to ambient.
The maximum power dissipation can be calculated by following formula:
P
D(MAX)
= ( T
J(MAX)
-T
A
) / R
thja
Where T
J(MAX)
is the maximum operation junction temperature 125
o
C, T
A
is the ambient
temperature and the R
thja
is the junction to ambient thermal resistance. The junction to ambient
thermal resistance (R
thja
is layout dependent) for ESOP-8 package (Exposed Pad) is 75
o
C/W on
standard JEDEC 51-7 (4 layers, 2S2P) thermal test board. The maximum power dissipation at T
A
= 25
o
C can be calculated by following formula:
P
D(MAX)
= (125
o
C - 25
o
C) / 75
o
C/W = 1.33W
The thermal resistance R
thja
of ESOP-8 (Exposed Pad) is determined by the package design
and the PCB design. However, the package design has been decided. If possible, it's useful to
increase thermal performance by the PCB design. The thermal resistance can be decreased by
adding copper under the expose pad of ESOP-8 package. We have to consider the copper
couldn't stretch infinitely and avoid the tin overflow
4
Advanced Power
Electronics Corp.
MARKING INFORMATION
ESOP-8
AP1270AMP
Part Number
Package Code
1270AMP
YWWSSS
Date Code (YWWSSS)
Y：Last Digit Of The Year
WW：Week
SSS：Sequence
5
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