19-2726; Rev 3; 12/03
3.3V, 16-Bit, 500Msps High Dynamic
Performance DAC with Differential LVDS Inputs
General Description
The MAX5888 is an advanced, 16-bit, 500Msps digital-
to-analog converter (DAC) designed to meet the
demanding performance requirements of signal synthe-
sis applications found in wireless base stations and
other communications applications. Operating from a
single 3.3V supply, this DAC offers exceptional dyna-
mic performance such as 76dBc spurious-free dynamic
range (SFDR) at f
OUT
= 40MHz. The DAC supports
update rates of 500Msps and a power dissipation of
only 250mW.
The MAX5888 utilizes a current-steering architecture,
which supports a full-scale output current range of 2mA
to 20mA, and allows a differential output voltage swing
between 0.1V
P-P
and 1V
P-P
.
The MAX5888 features an integrated 1.2V bandgap ref-
erence and control amplifier to ensure high accuracy
and low noise performance. Additionally, a separate
reference input pin enables the user to apply an exter-
nal reference source for optimum flexibility and to
improve gain accuracy.
The digital and clock inputs of the MAX5888 are
designed for differential low-voltage differential signal
(LVDS)-compatible voltage levels. The MAX5888 is
available in a 68-lead QFN package with an exposed
paddle (EP) and is specified for the extended industrial
temperature range (-40°C to +85°C).
Refer to the MAX5887 and MAX5886 data sheets for
pin-compatible 14- and 12-bit versions of the MAX5888.
o
500Msps Output Update Rate
o
Single 3.3V Supply Operation
o
Excellent SFDR and IMD Performance
SFDR = 76dBc at f
OUT
= 40MHz (to Nyquist)
IMD = -85dBc at f
OUT
= 10MHz
ACLR = 73dB at f
OUT
= 61MHz
o
2mA to 20mA Full-Scale Output Current
o
Differential, LVDS-Compatible Digital and Clock
Inputs
o
On-Chip 1.2V Bandgap Reference
o
Low 130mW Power Dissipation
o
68-Lead QFN-EP Package
Features
MAX5888
Ordering Information
PART
MAX5888AEGK
MAX5888EGK
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
PIN-
PACKAGE
68 QFN-EP*
68 QFN-EP*
*EP
= Exposed paddle.
Pin Configuration
DGND
DGND
DV
DD
B10N
B4P
B5P
B7P
B8P
B6P
B9P
TOP VIEW
Applications
Base Stations: Single-/Multicarrier UMTS,
CDMA, GSM
Communications: LMDS, MMDS, Point-to-Point
Microwave
Digital Signal Synthesis
Automated Test Equipment (ATE)
Instrumentation
B3P
B3N
B2P
B2N
B1P
B1N
B0P
B0N
DGND
1
2
3
4
5
6
7
8
9
68
67 66 65 64
63 62 61 60 59 58
57 56 55 54 53 52
EP
B10P
51
B11N
50
B11P
49
B12N
48
B12P
47
B13N
46
B13P
45
B14N
44
B14P
43
B15N
42
B15P
41
DGND
40
DV
DD
39
SEL0
38
N.C.
37
N.C.
36
N.C.
35
N.C.
B4N
B5N
B6N
B7N
B8N
MAX5888
DV
DD
10
VCLK
11
CLKGND
12
CLKP
13
CLKN
14
CLKGND
15
VCLK
16
PD
17
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
AGND
REFIO
DACREF
IOUTN
FSADJ
IOUTP
N.C.
AGND
AGND
AGND
B9N
AGND
AV
DD
AV
DD
AV
DD
AV
DD
QFN
________________________________________________________________
Maxim Integrated Products
AV
DD
N.C.
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
3.3V, 16-Bit, 500Msps High Dynamic
Performance DAC with Differential LVDS Inputs
MAX5888
ABSOLUTE MAXIMUM RATINGS
AV
DD
, DV
DD
, VCLK to AGND................................-0.3V to +3.9V
AV
DD
, DV
DD
, VCLK to DGND ...............................-0.3V to +3.9V
AV
DD
, DV
DD
, VCLK to CLKGND ...........................-0.3V to +3.9V
AGND, CLKGND to DGND....................................-0.3V to +0.3V
DACREF, REFIO, FSADJ to AGND.............-0.3V to AV
DD
+ 0.3V
IOUTP, IOUTN to AGND................................-1V to AV
DD
+ 0.3V
CLKP, CLKN to CLKGND...........................-0.3V to VCLK + 0.3V
B0P/B0N–B15P/B15N, SEL0,
PD to DGND ...........................................-0.3V to DV
DD
+ 0.3V
Continuous Power Dissipation (T
A
= +70°C)
68-Lead QFN-EP (derate 41.7mW/°C above +70°C) ...3333mW
Thermal Resistance (θ
JA
) ..............................................+24°C/W
Operating Temperature Range ..........................-40°C to +85°C
Junction Temperature .....................................................+150°C
Storage Temperature Range ............................-60°C to +150°C
Lead Temperature (soldering, 10s) ................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AV
DD
= DV
DD
= VCLK = 3.3V, AGND = DGND = CLKGND = 0, external reference, V
REFIO
= 1.25V, differential transformer-coupled
analog output, 50Ω double terminated (Figure 7), I
OUT
= 20mA, T
A
= T
MIN
to T
MAX
, unless otherwise noted.
≥+25°C
guaranteed by
production test, <+25°C guaranteed by design and characterization. Typical values are at T
A
= +25°C.)
PARAMETER
STATIC PERFORMANCE
Resolution
MAX5888A___, measured differentially,
T
A
≥
+25°C
MAX5888___, measured differentially,
T
A
≥
+25°C
Differential
Nonlinearity
Offset Error
Offset Drift
Full-Scale Gain Error
Gain Drift
Full-Scale Output Current
Min Output Voltage
Max Output Voltage
Output Resistance
Output Capacitance
DYNAMIC PERFORMANCE
Output Update Rate
Noise Spectral Density
Spurious-Free Dynamic Range to
Nyquist
f
CLK
f
CLK
= 300MHz
f
CLK
= 500MHz
SFDR
f
CLK
= 100MHz
f
OUT
= 16MHz, -12dB FS
f
OUT
= 16MHz, -12dB FS
f
OUT
= 1MHz, 0dB FS
f
OUT
= 1MHz, -6dB FS
f
OUT
= 1MHz, -12dB FS
1
-165
-164
88
89
85
dBc
500
Msps
dB FS/
Hz
R
OUT
C
OUT
I
OUT
GE
FS
External reference, T
A
≥
+25°C
Internal reference
External reference
(Note 1)
Single ended
Single ended
2
-0.5
1.1
1
5
-3.1
±100
±50
20
MAX5888A___, measured differentially,
T
A
≥
+25°C
MAX5888___, measured differentially,
T
A
≥
+25°C
OS
-0.025
-0.006
-0.008
16
±0.004
±0.006
±0.002
±0.003
±0.003
±50
+1.1
+0.025
%FS
ppm/°C
%FS
ppm/°C
mA
V
V
MΩ
pF
+0.006
% FS
+0.008
% FS
Bits
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Integral Nonlinearity
INL
DNL
2
_______________________________________________________________________________________
3.3V, 16-Bit, 500Msps High Dynamic
Performance DAC with Differential LVDS Inputs
ELECTRICAL CHARACTERISTICS (continued)
(AV
DD
= DV
DD
= VCLK = 3.3V, AGND = DGND = CLKGND = 0, external reference, V
REFIO
= 1.25V, differential transformer-coupled
analog output, 50Ω double terminated (Figure 7), I
OUT
= 20mA, T
A
= T
MIN
to T
MAX
, unless otherwise noted.
≥+25°C
guaranteed by
production test, <+25°C guaranteed by design and characterization. Typical values are at T
A
= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
f
CLK
= 100MHz
f
OUT
= 10MHz, -12dB FS
f
OUT
= 30MHz, -12dB FS
f
OUT
= 10MHz, -12dB FS
f
OUT
= 16MHz, -12dB FS,
f
CLK
= 200MHz T
A
≥
+25°C
SFDR
f
OUT
= 50MHz, -12dB FS
f
OUT
= 80MHz, -12dB FS
f
OUT
= 10MHz, -12dB FS
f
CLK
= 500MHz
f
OUT
= 30MHz, -12dB FS
f
OUT
= 50MHz, -12dB FS
f
OUT
= 80MHz, -12dB FS
Spurious-Free Dynamic Range,
25MHz Bandwidth
SFDR
f
CLK
= 150MHz f
OUT
= 20MHz, -12dB FS
f
CLK
= 100MHz
2-Tone IMD
TTIMD
f
OUT1
= 9MHz, -6dB FS,
f
OUT2
= 10MHz, -6dB FS
69
MIN
TYP
82
79
73
77
72
66
67
65
65
63
82
-85
dBc
-83
-78
dBc
dBc
dBc
MAX
UNITS
MAX5888
Spurious-Free Dynamic Range to
Nyquist
f
OUT1
= 49MHz, -12dB FS,
f
CLK
= 300MHz
f
OUT2
= 50MHz, -12dB FS
4-Tone IMD, 1MHz Frequency
Spacing, GSM Model
Adjacent Channel Leakage
Power Ratio, 4.1MHz Bandwidth,
WCDMA Model
Output Bandwidth
REFERENCE
Internal Reference Voltage Range
Reference Voltage Drift
Reference Input Compliance
Range
Reference Input Resistance
ANALOG OUTPUT TIMING
Output Fall Time
Output Rise Time
Output Voltage Settling Time
Output Propagation Delay
Glitch Energy
Output Noise
N
OUT
I
OUT
= 2mA
I
OUT
= 20mA
t
FALL
t
RISE
t
SETTLE
t
PD
90% to 10% (Note 3)
10% to 90% (Note 3)
Output settles to 0.025% FS (Note 3)
(Note 3)
V
REFIO
TCO
REF
V
REFIOCR
R
REFIO
0.125
1.13
FTIMD
f
CLK
= 300MHz f
OUT
= 32MHz, -12dB FS
f
CLK
=
184.32MHz
(Note 2)
ACLR
BW
-1dB
f
OUT
= 61.44MHz
73
450
1.22
±50
1.250
10
375
375
11
1.8
1
30
30
1.3
dB
MHz
V
ppm/°C
V
kΩ
ps
ps
ns
ns
pV-s
pA/√Hz
_______________________________________________________________________________________
3
3.3V, 16-Bit, 500Msps High Dynamic
Performance DAC with Differential LVDS Inputs
MAX5888
ELECTRICAL CHARACTERISTICS (continued)
(AV
DD
= DV
DD
= VCLK = 3.3V, AGND = DGND = CLKGND = 0, external reference, V
REFIO
= 1.25V, differential transformer-coupled
analog output, 50Ω double terminated (Figure 7), I
OUT
= 20mA, T
A
= T
MIN
to T
MAX
, unless otherwise noted.
≥+25°C
guaranteed by
production test, <+25°C guaranteed by design and characterization. Typical values are at T
A
= +25°C.)
PARAMETER
TIMING CHARACTERISTICS
Data to Clock Setup Time
Data to Clock Hold Time
Data Latency
Minimum Clock Pulse Width High
t
CH
CLKP, CLKN
Minimum Clock Pulse Width Low
t
CL
CLKP, CLKN
LVDS LOGIC INPUTS (B0N–B15N, B0P–B15P)
Differential Input Logic High
Differential Input Logic Low
Common-Mode Voltage Range
Differential Input Resistance
Input Capacitance
CMOS LOGIC INPUTS (PD, SEL0)
Input Logic High
Input Logic Low
Input Leakage Current
Input Capacitance
CLOCK INPUTS (CLKP, CLKN)
Differential Input Voltage Swing
Differential Input Slew Rate
Common-Mode Voltage Range
Input Resistance
Input Capacitance
POWER SUPPLIES
Analog Supply Voltage Range
Digital Supply Voltage Range
Clock Supply Voltage Range
Analog Supply Current
Digital Supply Current
Clock Supply Current
AV
DD
DV
DD
V
CLK
I
AVDD
I
DVDD
I
VCLK
f
CLK
= 100Msps, f
OUT
= 1MHz
Power-down
f
CLK
= 100Msps, f
OUT
= 1MHz
Power-down
f
CLK
= 100Msps, f
OUT
= 1MHz
Power-down
3.135
3.135
3.135
3.3
3.3
3.3
27
0.3
7
10
5.6
10
3.465
3.465
3.465
V
V
V
mA
mA
µA
mA
µA
V
CLK
SR
CLK
V
COM
R
CLK
C
CLK
Sine wave
Square wave
(Note 5)
≥1.5
≥0.5
>100
1.5
±20%
5
5
V
P-P
V/µs
V
kΩ
pF
V
IH
V
IL
I
IN
C
IN
-15
5
0.7
✕
DV
DD
0.3
✕
DV
DD
+15
V
V
µA
pF
V
IH
V
IL
V
COM
R
IN
C
IN
1.125
85
100
5
100
-100
1.375
125
t
SETUP
t
HOLD
Referenced to rising edge of clock (Note 4)
Referenced to rising edge of clock (Note 4)
-0.8
1.8
3.5
0.9
0.9
ns
ns
Clock
cycles
ns
ns
mV
mV
V
Ω
pF
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
4
_______________________________________________________________________________________
3.3V, 16-Bit, 500Msps High Dynamic
Performance DAC with Differential LVDS Inputs
ELECTRICAL CHARACTERISTICS (continued)
(AV
DD
= DV
DD
= VCLK = 3.3V, AGND = DGND = CLKGND = 0, external reference, V
REFIO
= 1.25V, differential transformer-coupled
analog output, 50Ω double terminated (Figure 7), I
OUT
= 20mA, T
A
= T
MIN
to T
MAX
, unless otherwise noted.
≥+25°C
guaranteed by
production test, <+25°C guaranteed by design and characterization. Typical values are at T
A
= +25°C.)
PARAMETER
Power Dissipation
Power-Supply Rejection Ratio
SYMBOL
P
DISS
PSRR
Power-down
AV
DD
= VCLK = DV
DD
= 3.3V
±5%
(Note 6)
-1
CONDITIONS
f
CLK
= 100Msps, f
OUT
= 1MHz
MIN
TYP
130
1
+1
MAX
UNITS
mW
%FS/V
MAX5888
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Nominal full-scale current I
OUT
= 32
✕
I
REF
.
This parameter does not include update-rate depending effects of sin(x)/x filtering inherent in the MAX5888.
Parameter measured single ended into a 50Ω termination resistor.
Parameter guaranteed by design.
A differential clock input slew rate of >100V/ms is required to achieve the specified dynamic performance.
Parameter defined as the change in midscale output caused by a ±5% variation in the nominal supply voltage.
Typical Operating Characteristics
(AV
DD
= DV
DD
= VCLK = 3.3V, external reference, V
REFIO
= 1.25V, R
L
= 50Ω, I
OUT
= 20mA, T
A
= +25°C, unless otherwise noted.)
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY (f
CLK
= 100MHz)
MAX5888 toc01
MAX5888 toc02
90
80
70
SFDR (dBc)
-6dB FS
-12dB FS
90
80
70
SFDR (dBc)
60
50
40
30
20
10
0
-6dB FS
90
80
70
SFDR (dBc)
60
50
40
30
20
10
0
0dB FS
-6dB FS
-12dB FS
60
50
40
30
20
10
0
0
0dB FS
-12dB FS
0dB FS
10
20
30
40
50
0
f
OUT
(MHz)
10 20 30 40 50 60 70 80 90 100
f
OUT
(MHz)
0
50
100
150
200
250
f
OUT
(MHz)
2-TONE INTERMODULATION DISTORTION
(f
CLK
= 100MHz)
MAX5888 toc04
2-TONE IMD vs. OUTPUT FREQUENCY
(1MHz CARRIER SPACING, f
CLK
= 300MHz)
MAX5888 toc05
2-TONE INTERMODULATION DISTORTION
(f
CLK
= 450MHz)
-10
-20
2-TONE IMD (dBm)
-30
-40
-50
-60
-70
-80
-90
2 x f
T1
- f
T2
2 x f
T2
- f
T1
f
T1
f
T2
A
OUT
= -6dB FS
BW = 5MHz
f
T1
= 79.2114MHz
f
T2
= 80.0903MHz
MAX5888 toc06
0
-10
-20
2-TONE IMD (dBm)
-30
-40
-50
-60
-70
-80
-90
-100
7
8
9
10
11
2 x f
T1
- f
T2
2 x f
T2
- f
T1
f
T1
f
T2
A
OUT
= -6dB FS
BW = 5MHz
f
T1
= 9.0252MHz
f
T2
= 10.0417MHz
-100
-90
TWO-TONE IMD (dBc)
-12dB FS
-80
-70
-60
-6dB FS
-50
-40
0
-100
0
25
50
75
100
77
78
79
80
81
82
f
OUT
(MHz)
f
OUT
(MHz)
12
f
OUT
(MHz)
_______________________________________________________________________________________
MAX5888 toc03
100
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY (f
CLK
= 200MHz)
100
100
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY (f
CLK
= 500MHz)
5
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