Datasheet> 器件分类 > 嵌入式处理器和控制器> 微控制器和处理器> Si5342D-A-GMR

Si5342D-A-GMR: 产品描述clock synthesizer / jitter cleaner 2-outputs 350mhz single pll jitter; 产品类别嵌入式处理器和控制器微控制器和处理器; 文件大小609KB，共54页; 制造商Silicon Laboratories Inc

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Si5342D-A-GMR概述

clock synthesizer / jitter cleaner 2-outputs 350mhz single pll jitter

Si5342D-A-GMR规格参数

参数名称	属性值
厂商名称	Silicon Laboratories Inc
包装说明	HVQCCN,
Reach Compliance Code	unknow
ECCN代码	EAR99
JESD-30 代码	S-XQCC-N44
长度	7 mm
端子数量	44
最高工作温度	85 °C
最低工作温度	-40 °C
最大输出时钟频率	350 MHz
封装主体材料	UNSPECIFIED
封装代码	HVQCCN
封装形状	SQUARE
封装形式	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
主时钟/晶体标称频率	750 MHz
座面最大高度	0.9 mm
最大供电电压	1.89 V
最小供电电压	1.71 V
标称供电电压	1.8 V
表面贴装	YES
技术	CMOS
温度等级	INDUSTRIAL
端子形式	NO LEAD
端子节距	0.5 mm
端子位置	QUAD
宽度	7 mm
uPs/uCs/外围集成电路类型	CLOCK GENERATOR, PROCESSOR SPECIFIC

文档解析

Si5345/44/42器件提供卓越的频率灵活性，能够基于任何输入频率生成多样化的输出时钟组合，满足复杂系统需求。关键特性包括输入频率范围8 kHz至750 MHz（差分）和8 kHz至250 MHz（LVCMOS），输出频率高达800 MHz（差分）和250 MHz（LVCMOS），抖动性能典型值低于100 fs（12 kHz–20 MHz）。可编程抖动衰减带宽（0.1 Hz至4 kHz）允许根据应用优化性能，同时支持DCO模式实现低至0.001 ppb的精细频率调整。输出兼容LVDS、LVPECL、LVCMOS和HCSL格式，输出-输出偏移小于100 ps，确保时序一致性。器件集成自动故障监控（LOS、OOF、LOL），并提供快速锁定功能（时间低于200 ms），在输出频率变化时无毛刺操作。通过I2C或SPI串行接口编程，结合非易失性存储器和ClockBuilder Pro软件，简化配置流程。适用于SONET/SDH线卡、广播视频系统和测试测量设备，其高灵活性减少外部时钟组件需求，降低设计复杂度。

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Si 5 3 4 5 / 4 4 /4 2

1 0 - C

H A N N E L

, A

-F

R E Q U E N C Y

, A

- O

U T P U T

I T T E R

T T E N U A T O R

LOC K

U LT IP L IE R

Features



IN3/FB_IN



Generates any combination of



output frequencies from any input



frequencies



Input frequency range:



Differential: 8 kHz to 750 MHz





LVCMOS: 8 kHz to 250 MHz

Output frequency range:





Differential: up to 800 MHz



LVCMOS: up to 250 MHz

Jitter performance:



<100 fs typ (12 kHz–20 MHz)

Programmable jitter attenuation



bandwidth: 0.1 Hz to 4 kHz



Meets G.8262 EEC Opt 1, 2 (SyncE)



Highly configurable outputs

compatible with LVDS, LVPECL,

LVCMOS, HCSL, or programmable



voltage swing and common mode

Status monitoring (LOS, OOF, LOL)



Hitless input clock switching:



automatic or manual



Locks to gapped clock inputs



Automatic free-run and holdover

modes

Optional zero delay mode

Fastlock feature: <200 ms lock time

Glitchless on the fly output

frequency changes

DCO mode: as low as 0.001 ppb

steps.

Core voltage



: 1.8 V ±5%



DDA

3.3 V ±5%

Independent output supply pins:

3.3 V, 2.5 V, or 1.8 V

Output-output skew: <100 ps

Serial interface:

or SPI

In-circuit programmable with

non-volatile OTP memory

ClockBuilder Pro

software

simplifies device configuration

Si5345: 4 input, 10 output, 64 QFN

Si5344: 4 input, 4 output, 44 QFN

Si5342: 4 input, 2 output, 44 QFN

Temperature range: –40 to +85 °C

Pb-free, RoHS-6 compliant

Ordering Information:

See section 7

Pin Assignments

Si5345

Top View

VDDO9

VDDO8

RSVD

OUT8

VDDO7

OUT9

OUT8

OUT7

IN1

IN_SEL0

IN_SEL1

RSVD

RST

INTR

VDDA

IN2

OUT7

VDD

IN0

FINC

LOL

VDD

OUT6

VDDO6

OUT5

VDDO5

I2C_SEL

OUT4

VDDO4

OUT3

VDDO3

GND

Pad

Applications



OTN Muxponders and



Transponders



10/40/100G network line cards



GbE/10GbE/100GbE Synchronous



Ethernet

IN3/FB_IN

VDD

I2C_SEL

IN_SEL1

IN1

VDDO3

Carrier Ethernet switches

SONET/SDH Line Cards

Broadcast video

Test and measurement

SCLK

RSVD

SDA/SDIO

A1/SDO

RSVD

FDEC

OUT0

OUT1

OUT2

VDDO0

VDDO1

Si5344 44QFN

Top View

OUT3

IN0

VDD

VDDO2

A0/CS

OUT2

INTR

VDD

OUT2

VDDO2

LOS_XAXB

LOL

VDDS

OUT1

VDDO1

Description

These jitter attenuating clock multipliers combine fourth-generation DSPLL and

MultiSynth™ technologies to enable any-frequency clock generation and jitter

attenuation for applications that require the highest level of jitter performance.

These devices are programmable via a serial interface with in-circuit

programmable non-volatile memory (NVM) so that they always power up with a

known frequency configuration. They support free-run, synchronous, and

holdover modes of operation, and offer both automatic and manual input clock

switching. The loop filter is fully integrated on-chip eliminating the risk of potential

noise coupling associated with discrete solutions. Further, the jitter attenuation

bandwidth is digitally programmable providing jitter performance optimization at

the application level. Programming the Si5345/44/42 is made easy with Silicon

Labs’

ClockBuilderPro

software. Factory preprogrammed devices are also

available.

IN1

IN_SEL0

VDDA

IN2

GND

Pad

A1/SDO

OUT0

SDA/SDIO

Si5342 44QFN

Top View

IN3/FB_IN

VDD

I2C_SEL

IN_SEL1

VDDS

LOS3

LOS2

IN0

VDD

VDDO0

A0/CS

SCLK

OUT0

VDD

RST

IN1

IN_SEL0

VDDA

IN2

INTR

VDD

LOS1

LOS0

VDDS

LOS_XAXB

LOL

VDDS

OUT1

VDDO1

GND

Pad

OUT0

VDD

SDA/SDIO

A1/SDO

VDDO0

Preliminary Rev. 0.9 7/14

A0/CS

SCLK

OUT0

RST

This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

VDD

Si5345/44/42

Si5345/44/42

ABLE

ON TENTS

1. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

2. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

3. Detailed Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.1. Frequency Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.2. DSPLL Loop Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.3. Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.4. External Reference (XA/XB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.5. Digitally Controlled Oscillator (DCO) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.6. Inputs (IN0, IN1, IN2, IN3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.7. Fault Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

4.8. Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

4.9. Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

4.10. In-Circuit Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

4.11. Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

4.12. Custom Factory-Preprogrammed Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

5. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

5.1. Addressing Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

5.2. High-Level Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

6. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

7. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

8. Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

8.1. Si5345 9x9 mm 64-QFN Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

8.2. Si5344 and Si5342 7x7 mm 44-QFN Package Diagram . . . . . . . . . . . . . . . . . . . . . . 48

9. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

10. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

11. Device Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Appendix—Advance Product Information Revision History . . . . . . . . . . . . . . . . . . . . . . . 53

Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

Preliminary Rev. 0.9

Si5342D-A-GMR

Si5342D-A-GMR在线购买

Si5342D-A-GMR概述

Si5342D-A-GMR规格参数

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