IDT74SSTUA32866
1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST
COMMERCIAL TEMPERATURE RANGE
1.8V CONFIGURABLE
BUFFER WITH ADDRESS-
PARITY TEST
FEATURES:
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IDT74SSTUA32866
1.8V Operation
SSTL_18 style clock and data inputs
Differential CLK input
Configurable as 25-bit 1:1 or 14-bit 1:2 registered buffer
Control inputs compatible with LVCMOS levels
Flow-through architecture for optimum PCB design
Latch-up performance exceeds 100mA
ESD >2000V per MIL-STD-883, Method 3015; >200V using
machine model (C = 200pF, R = 0)
Checks parity on data inputs
Maximum operating frequency: 410MHz
Optimized for DDR2 - 400 / 533 / 667 (PC2 - 3200 / 4300 / 5300)
JEDEC R/C E, F, G, H, and J
Available in 96-pin LFBGA package
APPLICATIONS:
• Along with CSPUA877 DDR2 PLL, provides complete solution for
DDR2 DIMMs
DESCRIPTION:
This 25-bit 1:1 / 14-bit 1:2 configurable registered buffer is designed for
1.7V to 1.9V V
DD
operation. In the 1:1 pinout configuration, only one device
per DIMM is requred to drive nine SDRAM loads. In the 1:2 pinout
configuration, two devices per DIMM are required to drive eighteen
SDRAM loads. All inputs are SSTL_18, except reset (RESET) and control
(Cn) inputs, which are LVCMOS. All outputs are edge-controlled circuits
optimized for unterminated DIMM loads, and meet SSTL_18 specifications,
except the open-drain error (QERR) output.
The SSTUA32866 operates from a differential clock (CLK and
CLK).
Data are registered at the crossing of CLK going high and
CLK
going low.
Parity is checked on the parity bit (PAR_IN) input which arrives one cycle
after the input data to which it applies. The
QERR
output is open drain.
When used as a single device, the C0 and C1 inputs are tied low. In this
configuration, the partial-parity-out (PPO) and
QERR
signals are produced
two clock cycles after the corresponding data output.
When used in pairs, the C0 input of the first register is tied low and the
C0 input of the second register is tied high. The C1 input of both registers
are tied high. The
QERR
output of the first SSTUA32866 is left floating and
the valid error information is latched on the
QERR
output of the second
SSTUA32866.
If an error occurs and the
QERR
output is driven low, it stays latched low
for two clock cycles or until
RESET
is driven low. The DIMM-dependent
signals (DODT, DCKE,
DCS,
and
CSR)
are not included in the parity check.
The CO input controls the pinout configuration of the 1:2 pinout from
register A configuration (when low) to register B configuration (when high).
The C1 input controls the pinout configurationfrom 25-bit 1:1 (when low) to
14-bit 1:2 (when high). C0 and C1 should not be switched during normal
operation. They should be hard-wired to a valid low or high level to
configure the register in the desired mode. In the 25-bit 1:1 pinout
configuration, the A6, D6, and H6 terminals are driven low and should not
be used.
The device supports low-power standby operation. When
RESET
is low,
the differential input recievers are disabled, and undriven (floating) data,
clock, and reference voltage (V
REF
) inputs are allowed. In addition, when
RESET
is low, all registers are reset and all outputs except
QERR
are forced
low. The LVCMOS
RESET
and Cn inputs always must be held at a valid
logic high or low level.
There are two V
REF
pins (A3 and T3). However, it is necessary to only
connect one of the two V
REF
pins to the external V
REF
power supply. An
unused V
REF
pin should be terminated with a V
REF
coupling capacitor.
The device also supports low-power active operation by monitoring both
system chip select (DCS and
CSR)
inputs and will gate the Qn and PPO
outputs from changing states when both
DCS
and
CSR
inputs are high. If
either
DCS
or
CSR
input is low, the Qn and PPO outputs will function
normally. Also, if the internal low power signal (LPS1) is high, the device
will gate the
QERR
output from changing states. If
LPS1
is low, the
QERR
output will function normally. The
RESET
input has priority over the
DCS
and
CSR
control and when driven low will force the Qn and PPO outputs
low, and the
QERR
output high. If the
DCS
control functionality is not desired,
then the
CSR
input can be hard-wired to ground, in which case the setup-
time requirement for
DCS
would be the same as for the other D data inputs.
To control the low-power mode with
DCS
only, then the
CSR
input should
be pulled up to V
DD
through a pullup resistor.
To ensure defined outputs from the register before a stable clock has been
supplied,
RESET
must be held in the low state during power up.
COMMERCIAL TEMPERATURE RANGE
1
c
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JUNE 2005
DSC 6382/9
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