Freescale Semiconductor
Technical Data
Document Number: MC33810
Rev. 11.0, 8/2014
Automotive Engine Control IC
The 33810 is an eight channel output driver IC intended for automotive engine
control applications. The IC consists of four integrated low-side drivers and four
low-side gate pre-drivers. The low-side drivers are suitable for driving fuel
injectors, solenoids, lamps, and relays. The four gate pre-drivers can function
either as ignition IGBT gate pre-drivers or as general purpose MOSFET gate
pre-drivers. This device is powered by SMARTMOS technology.
When configured as ignition IGBT gate pre-drivers, additional features are
enabled such as spark duration, dwell time, and ignition coil current sense.
When configured as a general purpose gate pre-driver (GPGD), the 33810
provides external MOSFETs with short-circuit protection, inductive flyback
protection and diagnostics. The device is packaged in a 32 pin (0.65mm pitch)
exposed pad SOIC.
Features
• Designed to operate over the range of 4.5 V
VPWR
36 V
• Quad ignition IGBT or MOSFET gate pre-driver with parallel/SPI and/or PWM
control
• Quad injector driver with parallel/SPI control
• Interfaces directly to MCU using 3.3 V / 5.0 V SPI protocol
• Injector driver current limit - 4.5 A max.
• Independent fault protection and diagnostics
• V
PWR
standby current 10
A
max.
33810
ENGINE CONTROL
EK SUFFIX (Pb-FREE)
98ASA10556D
32 PIN SOICW -EP
Applications
• Automotive
• Motorcycle engine control unit (ECU) and small
engine control
• PSI5 airbag system
• Central gateway/in-vehicle networking
• Braking and stability control
• Gasoline engine management
• Hybrid electric vehicle (HEV) inverter controller
V
BAT
V
DD
VPWR
VDD
33810
OUT0
OUT1
OUT2
OUT3
GND
FB0
GD0
FB1
GD1
FB2
GD2
FB3
GD3
RSP
RSN
V
BAT
V
BAT
V
BAT
V
BAT
V
BAT
MCU
MOSI
SCLK
CS
MISO
ETPU
ETPU
ETPU
ETPU
GPIO
ETPU
ETPU
ETPU
SI
SCLK
CS
SO
DIN0
DIN3
GIN0
GIN3
OUT EN
SPKDUR
NOMI
MAXI
V
BAT
V
BAT
V
BAT
Figure 1. MC33810 Simplified Application Diagram
© Freescale Semiconductor, Inc., 2006 - 2014. All rights reserved.
ORDERABLE PARTS
ORDERABLE PARTS
This section describes the part numbers available to be purchased along with their differences. Valid orderable part numbers are
provided on the web. To determine the orderable part numbers for this device, go to
http://www.freescale.com
and perform a part number
search for the following device numbers.
Table 1. Orderable Part Variations
Part Number
MCZ33810EK
Notes
(1)
Temperature (T
A
)
-40 °C to 125 °C
32 SOICW-EP
Package
Notes
1. To order parts in Tape & Reel, add the R2 suffix to the part number.
33810
2
Analog Integrated Circuit Device Data
Freescale Semiconductor
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
VPWR
VDD
V
DD
~50 µA
V
DD
~50 µA
LOGIC CONTROL
VPWR, VDD
V8.0 Analog
V2.5 Logic
POR, Overvoltage
Undervoltage
Oscillator
Bandgap
Bias
V2.5
Outputs 0 to 3
CS
SI
SCLK
OUTEN
~15 µA
V
DD
~15 µA
SPI
INTERFACE
SO
DIN0
~50 µA
PARALLEL
CONTROL
Gate Control
Current Limit
Temperature Limit
Short/Open
VOC1
OUT0
OUT1
OUT2
OUT3
75 µA
DIN1
~50 µA
+
–
lLimit
R
S
DIN2
~50 µA
PWM
CONTROLLER
Exposed
Pad
+
–
DIN3
~50 µA
NOMI,MAXI
DAC
SPARK DURATION
Open Secondary
SPARK
DAC
~50 µA
SPI
SPI
100 µA
VLVC
+
–
GIN0
~50 µA
V
PWR
FB0
FB1
FB2
FB3
GPGD
Only
GIN1
VOC
GIN2
~50 µA
GATE DRIVE
CONTROL
Low V
Clamp
GPGD
Clamp
GIN3
~50 µA
VDD
~5 0µA
NOMI
+
–
GD0
GD1
GD2
GD3
DAC
SPKDUR
MAXI
+
–
RSP
DAC
RSN
NOMI
MAXI
Exposed Pad
GND
Figure 2. 33810 Simplified Internal Block Diagram
33810
Analog Integrated Circuit Device Data
Freescale Semiconductor
3
PIN CONNECTIONS
PIN CONNECTIONS
Transparent Top View
OUT0
FB0
GD0
CS
SCLK
SI
SO
VDD
OUTEN
DIN0
DIN1
DIN2
DIN3
GD1
FB1
OUT1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
GND
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OUT2
FB2
GD2
MAXI
NOMI
RSN
RSP
VPWR
GIN0
GIN1
GIN2
GIN3
SPKDUR
GD3
FB3
OUT3
Figure 3. 33810 Pin Connections
A functional description of each pin can be found in the
Functional Pin Description
section beginning on
page 14.
Table 2. 33810 Pin Definitions
Pin Number
1, 16, 32, 17
2, 15, 31, 18
Pin Name
OUT0, OUT1,
OUT2, OUT3
FB0, FB1,
FB2, FB3
GD0, GD1,
GD2, GD3
Pin Function
Output
Input
Formal Name
Low-side Injector
Driver Output
Feedback Voltage
Sense
Gate Drive Output
Definition
These pins are the Open drain low-side injector driver outputs.
In IGBT ignition gate pre-driver mode, these feedback inputs monitor the IGBT's
collector voltage to provide the spark duration timer control signal.
IGBT/GPGD outputs are controlled by GIN0 - 3. Pull-up and pull-down current
sources are used to provide a controlled slew rate to an external IGBT or MOSFET
connected as a low-side driver.
The Chip Select input pin is an active low signal sent by the MCU to indicate the
device is being addressed. This input requires CMOS logic levels and has an
internal active pull-up current source.
The SCLK input pin is used to clock the serial data on the SI and SO pins in and
out while being addressed by the CS.
The SI input pin is used to receive serial data from the MCU.
The SO output pin is used to transmit serial data from the device to the MCU.
The VDD input supply voltage determines the interface voltage levels between the
device and the MCU, and is used to supply power to the Serial Out buffer (SO),
SPKDUR buffer, MAXI, NOMI, and pull-up current source for the Chip Select (CS).
The Output Enable pin (OUTEN) is an active low input. When the OUTEN pin is low,
the device outputs are active. The outputs are disabled when OUTEN is high.
Active high input control for injector outputs OUT0 - 3. The parallel input data is
logically ORed with the corresponding SPI input data register contents.
3, 14, 30,19
Output
4
CS
Input
Chip Select
5
6
7
8
SCLK
SI
SO
VDD
Input
Input
Output
Input
Serial Clock Input
Serial Input Data
Serial Output Data
Digital Logic Supply
Voltage
Output Enable
Driver Input 0, Driver
Input 1, Driver Input 2,
Driver Input 3
9
OUTEN
DIN0,DIN1,
DIN2,DIN3
SPKDUR
Input
10, 11, 12, 13
Input
20
Output
This pin is the Spark Duration Output. This open drain output is low while feedback
Spark Duration Output inputs FB0 - 3 are above the programmed spark detection threshold.
Gate Driver Input 0
Gate Driver Input 1
Gate Driver Input 2
Gate Driver Input 3
These pins are the active high input control for IGBT/GPGD outputs GD0 - 3. The
parallel input data is logically ORed with the corresponding SPI input data register
contents in GPGD mode only.
24, 23, 22, 21
GIN0,GIN1,
GIN2,GIN3
VPWR
Input
25
Input
Analog Supply Voltage VPWR is the main voltage input for all internal analog bias circuitry.
33810
4
Analog Integrated Circuit Device Data
Freescale Semiconductor
PIN CONNECTIONS
Table 2. 33810 Pin Definitions (continued)
Pin Number
26
27
28
Pin Name
RSP
RSN
NOMI
Pin Function
Input
Input
Output
Formal Name
Resistor Sense
Positive
Resistor Sense
Negative
Nominal Ignition Coil
Current
Definition
This pin is the Positive input of a current sense amplifier.
This pin is the Negative input of a current sense amplifier.
This pin is the Nominal Ignition Coil Current output flag. This output is asserted
when the IGBT Collector-Emitter current exceeds the level selected by the DAC.
This pin is the Maximum Ignition Coil Current output flag. This output is asserted
when the IGBT Collector-Emitter current exceeds the selected level of the DAC.
This signal also latches off the gate pre-drive outputs when configured as a GPGD.
The MAXI current level is determined by the voltage drop across an external sense
resistor connected to pins RSP and RSN.
The exposed pad is the only ground reference for analog, digital and power ground
connections. As such, it must be soldered directly to a low-impedance ground plane
for both electrical and thermal considerations. For more information about this
package, see application note
AN2409
on the Freescale web site,
www.freescale.com
29
MAXI
Output
Maximum Ignition Coil
Current
Exposed Pad
(bottom of
package)
GND
Ground
Ground
33810
Analog Integrated Circuit Device Data
Freescale Semiconductor
5
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