S25FL256L/S25FL128L
256 Mbit (32 Mbyte)/128 Mbit (16 Mbyte),
3.0 V FL-L Flash Memory
General Description
The Cypress FL-L Family devices are Flash non-volatile memory products using:
– Floating Gate technology
– 65 nm process lithography
The FL-L family connects to a host system via a Serial Peripheral Interface (SPI). Traditional SPI single bit serial input and output
(Single I/O or SIO) is supported as well as optional two bit (Dual I/O or DIO) and four bit wide Quad I/O (QIO) and Quad Peripheral
Interface (QPI) commands. In addition, there are Double Data Rate (DDR) read commands for QIO and QPI that transfer address
and read data on both edges of the clock.
The architecture features a Page Programming Buffer that allows up to 256-bytes to be programmed in one operation and provides
individual 4KB sector, 32KB half block, 64KB block, or entire chip erase.
By using FL-L family devices at the higher clock rates supported, with Quad commands, the instruction read transfer rate can match
or exceed traditional parallel interface, asynchronous, NOR Flash memories, while reducing signal count dramatically.
The FL-L family products offer high densities coupled with the flexibility and fast performance required by a variety of mobile or
embedded applications. Provides an ideal storage solution for systems with limited space, signal connections, and power. These
memories offer flexibility and performance well beyond ordinary serial flash devices. They are ideal for code shadowing to RAM,
executing code directly (XIP), and storing re-programmable data.
Features
Serial Peripheral Interface (SPI) with Multi-I/O
– Clock polarity and phase modes 0 and 3
– Double Data Rate (DDR) option
– Quad peripheral Interface (QPI) option
– Extended Addressing: 24- or 32-bit address options
– Serial Command subset and footprint compatible with S25FL-A,
S25FL1-K, S25FL-P, S25FL-S and S25FS-S SPI families
– Multi I/O Command subset and footprint compatible with S25FL-P,
S25FL-S and S25FS-S SPI families
Read
– Commands: Normal, Fast, Dual I/O, Quad I/O, DualO, QuadO,
DDR Quad I/O.
– Modes: Burst Wrap, Continuous (XIP), QPI
– Serial Flash Discoverable Parameters (SFDP) for configuration
information.
Program Architecture
– 256 Bytes Page Programming buffer3.0 V FL-L Flash Memory
– Program suspend and resume
Erase Architecture
– Uniform 4KB Sector Erase
– Uniform 32KB Half Block Erase
– Uniform 64KB Block Erase
– Chip erase
– Erase suspend and resume
100,000 Program/Erase Cycles
20 Year Data Retention
Security features
– Status and Configuration Register Protection
– Four Security Regions of 256 bytes each outside the main Flash
array
– Legacy Block Protection: Block range
– Individual and Region Protection
– Individual Block Lock: Volatile individual Sector/Block
– Pointer Region: Non-Volatile Sector/Block range
– Power Supply Lock-down, Password, or Permanent protection
of Security Regions 2 and 3 and Pointer Region
Technology
– 65 nm Floating Gate Technology
Single Supply Voltage with CMOS I/O
– 2.7 V to 3.6 V
Temperature Range / Grade
– Industrial (–40°C to +85°C)
– Industrial Plus (–40°C to +105°C)
– Extended (–40°C to +125°C)
– Automotive, AEC-Q100 Grade 3 (–40°C to +85°C)
– Automotive, AEC-Q100 Grade 2 (–40°C to +105°C)
– Automotive, AEC-Q100 Grade 1 (–40°C to +125°C)
Packages (all Pb-free)
– 8-pin SOIC 208 mil (SOC008) — S25FL128L only
– WSON 5
6 mm (WND008) — S25FL128L only
– WSON 6
8 mm (WNG008) — S25FL256L only
– 16-pin SOIC 300 mil (SO3016) — S25FL256L only
– BGA-24 6
8 mm
– 5
5 ball (FAB024) footprint
– 4
6 ball (FAC024) footprint
Cypress Semiconductor Corporation
Document Number: 002-00124 Rev. *C
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised September 26, 2016
S25FL256L/S25FL128L
Performance Summary
Maximum Read Rates SDR
Command
Read
Fast Read
Dual Read
Quad Read
Clock Rate (MHz)
50
133
133
133
MBps
6.25
16.5
33
66
Maximum Read Rates DDR
Command
DDR Quad Read
Clock Rate (MHz)
66
MBps
66
Typical Program and Erase Rates
Operation
Page Programming
4 KBytes Sector Erase
32 KBytes Half Block Erase
64 KBytes Block Erase
KBytes/s
854
80
168
237
Typical Current Consumption,
–
40°C to +85°C
Operation
Fast Read 5MHz
Fast Read 10 MHz
Fast Read 20 MHz
Fast Read 50 MHz
Fast Read 108 MHz
Fast Read 133 MHz
Quad I/O / QPI Read 108 MHz
Quad I/O / QPI Read 133 MHz
Quad I/O / QPI DDR Read 33MHz
Quad I/O / QPI DDR Read 66MHz
Program
Erase
Standby SPI
Standby QPI
Deep Power Down
Typical Current
10
10
10
15
25
30
25
30
15
30
40
40
20
60
2
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
µA
µA
µA
Document Number: 002-00124 Rev. *C
Page 2 of 154
S25FL256L/S25FL128L
Contents
General Description
............................................................. 1
Features.................................................................................
1
1.
1.1
2.
2.1
2.2
2.3
2.4
3.
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
3.10
3.11
3.12
3.13
3.14
4.
4.1
5.
5.1
5.2
5.3
5.4
6.
6.1
6.2
6.3
6.4
6.5
6.6
7.
7.1
7.2
7.3
7.4
7.5
7.6
7.7
8.
8.1
8.2
Product Overview
........................................................ 4
Migration Notes.............................................................. 4
Connection Diagrams..................................................
SOIC 16-Lead ................................................................
8 Connector Packages...................................................
BGA Ball Footprint .........................................................
Special Handling Instructions for FBGA Packages........
5
5
5
6
7
8.3
8.4
8.5
8.6
8.7
8.8
8.9
8.10
8.11
8.12
9.
9.1
9.2
Register Access Commands......................................... 68
Read Memory Array Commands .................................. 81
Program Flash Array Commands ................................. 90
Erase Flash Array Commands...................................... 92
Security Regions Array Commands.............................. 99
Individual Block Lock Commands ............................... 101
Pointer Region Command........................................... 105
Individual and Region Protection (IRP) Commands ... 106
Reset Commands ....................................................... 111
Deep Power Down Commands................................... 112
Data Integrity
............................................................. 115
Erase Endurance ........................................................ 115
Data Retention ............................................................ 115
Signal Descriptions
..................................................... 8
Input/Output Summary................................................... 8
Multiple Input / Output (MIO).......................................... 9
Serial Clock (SCK) ......................................................... 9
Chip Select (CS#) .......................................................... 9
Serial Input (SI) / IO0 ..................................................... 9
Serial Output (SO) / IO1................................................. 9
Write Protect (WP#) / IO2 .............................................. 9
IO3 / RESET# .............................................................. 10
RESET# ....................................................................... 10
Voltage Supply (V
DD
)................................................... 10
Supply and Signal Ground (V
SS
) ................................. 10
Not Connected (NC) .................................................... 10
Reserved for Future Use (RFU)................................... 11
Do Not Use (DNU) ....................................................... 11
Block Diagrams..........................................................
12
System Block Diagrams............................................... 12
Signal Protocols.........................................................
SPI Clock Modes .........................................................
Command Protocol ......................................................
Interface States............................................................
Data Protection ............................................................
15
15
16
21
25
10. Software Interface Reference
.................................. 116
10.1 JEDEC JESD216B Serial Flash Discoverable Parameters
.....................................................................................116
10.2 Device ID Address Map .............................................. 124
10.3 Initial Delivery State .................................................... 124
11.
11.1
11.2
11.3
11.4
11.5
11.6
12.
12.1
12.2
12.3
12.4
12.5
12.6
Electrical Specifications...........................................
125
Absolute Maximum Ratings ........................................ 125
Latchup Characteristics .............................................. 125
Thermal Resistance .................................................... 125
Operating Ranges....................................................... 126
Power-Up and Power-Down ....................................... 127
DC Characteristics ...................................................... 129
Timing Specifications...............................................
132
Key to Switching Waveforms ...................................... 132
AC Test Conditions ..................................................... 132
Reset .......................................................................... 133
SDR AC Characteristics.............................................. 136
DDR AC Characteristics ............................................. 139
Embedded Algorithm Performance Tables ................. 141
Address Space Maps.................................................
26
Overview ...................................................................... 26
Flash Memory Array..................................................... 26
ID Address Space ........................................................ 27
JEDEC JESD216 Serial Flash Discoverable Parameters
(SFDP) Space.............................................................. 27
Security Regions Address Space ................................ 27
Registers...................................................................... 28
Data Protection
..........................................................
Security Regions..........................................................
Deep Power Down .......................................................
Write Enable Commands .............................................
Write Protect Signal .....................................................
Status Register Protect (SRP1, SRP0)........................
Array Protection ...........................................................
Individual and Region Protection .................................
44
44
44
45
46
46
47
54
13. Ordering Information
................................................ 142
13.1 Ordering Part Number................................................. 142
14.
14.1
14.2
14.3
14.4
14.5
14.6
15.
15.1
15.2
15.3
15.4
13.
Physical Diagrams
.................................................... 145
SOIC 16-Lead, 300-mil Body Width (SO3016) ........... 145
SOIC 8-Lead, 208 mil Body Width (SOC008)............. 146
WSON 8-Contact 5 x 6 mm Leadless (WND008) ....... 147
WSON 8-Contact 6 x 8 mm Leadless (WNG008)....... 148
Ball Grid Array 24-ball 6 x 8 mm (FAB024)................. 149
Ball Grid Array 24-ball 6 x 8 mm (FAC024) ................ 150
Other Resources
....................................................... 151
Glossary...................................................................... 151
Link to Cypress Flash Roadmap................................. 152
Link to Software .......................................................... 152
Link to Application Notes ............................................ 152
Document History
..................................................... 153
Commands
................................................................. 59
Command Set Summary.............................................. 59
Identification Commands ............................................. 65
Document Number: 002-00124 Rev. *C
Page 3 of 154
S25FL256L/S25FL128L
1. Product Overview
1.1
1.1.1
Migration Notes
Features Comparison
The FL-L family is command subset and footprint compatible with prior generation FL-S, FL1-K and FL-P families.
Table 1.1
Cypress SPI Families Comparison
Parameter
Technology Node
Architecture
Release Date
Density
Bus Width
Supply Voltage
Normal Read Speed
Fast Read Speed
Dual Read Speed
Quad Read Speed
Quad Read Speed (DDR)
Program Buffer Size
Erase Sector/Block Size
Parameter Sector Size
Sector / Block Erase Rate (typ.)
256Mb
x1, x2, x4
2.7 V - 3.6 V
6MB/s (50MHz)
16.5MB/s (133MHz)
33MB/s (133MHz)
66MB/s (133MHz)
66MB/s (66MHz)
256B
4KB / 32KB / 64KB
-
80 KB/s (4KB)
168 KB/s (32KB
237KB/s (64KB)
Page Programming Rate (typ.)
Security Region / OTP
Individual and Region Protection or
Advanced Sector Protection
Erase Suspend/Resume
Program Suspend/Resume
Operating Temperature
854KB/s (256B)
1024B
Yes
Yes
Yes
–40°C to +85°C
–40°C to +105°C
–40°C to +125°C
Note:
1. Refer to individual data sheets for further details
1.2 MB/s (256B)
1.5 MB/s (512B)
1024B
Yes
Yes
Yes
–40°C to +85°C
–40°C to +105°C
500 KB/s
FL-L
65nm
Floating Gate
FL-S
65nm
MirrorBit
®
Eclipse™
In Production
128Mb - 1Gb
x1, x2, x4
2.7 V - 3.6 V / 1.65 V - 3.6 V V
IO
6MB/s (50MHz)
17MB/s (133MHz)
26MB/s (104MHz)
52MB/s (104MHz)
80MB/s (80MHz)
256B / 512B
64KB / 256KB
4KB (option)
FL1-K
90nm
Floating Gate
In Production
4Mb - 64Mb
x1, x2, x4
2.7 V - 3.6 V
6MB/s (50MHz)
13MB/s (108MHz)
26MB/s (108MHz)
52MB/s (108MHz)
–
256B
4KB / 64KB
–
136 KB/s (4KB)
437 KB/s (64KB)
365 KB/s
768B (3
256B)
No
Yes
Yes
–40°C to +85°C
FL-P
90nm
MirrorBit
®
In Production
32Mb - 256Mb
x1, x2, x4
2.7 V - 3.6 V
5MB/s (40MHz)
13MB/s (104MHz)
20MB/s (80MHz)
40MB/s (80MHz)
–
256B
64KB / 256KB
4KB
130 KB/s
170 KB/s
506B
No
No
No
–40°C to +85°C
–40°C to +105°C
Document Number: 002-00124 Rev. *C
Page 4 of 154
S25FL256L/S25FL128L
2. Connection Diagrams
2.1
SOIC 16-Lead
Figure 2.1
16-Lead SOIC Package (SO3016), Top View
IO3 / RESET#
VDD
RESET#
NC
NC
RFU
CS#
SO / IO1
1
2
3
4
16
15
14
13
SCK
SI / IO0
RFU
DNU
DNU
DNU
VSS
WP# / IO2
SOIC 16
5
6
7
8
12
11
10
9
Note:
1. The RESET# and IO3 / RESET# inputs have an internal pull-up and may be left unconnected in the system if quad mode, mode and hardware
reset are not in use.
2.2
8 Connector Packages
Figure 2.2
8-Pin Plastic Small Outline Package (SOIC8)
CS#
SO
/ IO
1
W P# / IO 2
V SS
1
2
8
7
VDD
IO 3 / R ESET#
SCK
SI / IO 0
SO IC
3
4
6
5
Document Number: 002-00124 Rev. *C
Page 5 of 154
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