74LV595
8-bit serial-in/serial-out or parallel-out shift register; 3-state
Rev. 4 — 18 March 2016
Product data sheet
1. General description
The 74LV595 is an 8 stage serial shift register with a storage register and 3-state outputs.
Both the shift and storage register have separate clocks. It is a low-voltage Si-gate CMOS
device and is pin and functionally compatible with the 74HC595 and 74HCT595.
Data is shifted on the positive-going transitions of the SHCP input. The data in the shift
register is transferred to the storage register on a positive-going transition of the STCP
input. If both clocks are connected together, the shift register will always be one clock
pulse ahead of the storage register.
The shift register has a serial input (DS) and a serial output (Q7S) for cascading the
device. It is also provided with an asynchronous reset input MR (active LOW) for all 8 shift
register stages. The storage register has 8 parallel 3-state bus driver outputs. Data in the
storage register appears at the output whenever the output enable input (OE) is LOW.
2. Features and benefits
Optimized for low voltage applications: 1.0 V to 3.6 V
Accepts TTL input levels between V
CC
= 2.7 V and V
CC
= 3.6 V
Typical output ground bounce < 0.8 V at V
CC
= 3.3 V and T
amb
= 25
C
Typical HIGH-level output voltage (V
OH
) undershoot: > 2 V at V
CC
= 3.3 V and
T
amb
= 25
C
Specified from
40 C
to +85
C
and from
40 C
to +125
C
Has a shift register with direct clear
Multiple package options
Output capability:
Parallel outputs; bus driver
serial output; standard
ESD protection:
HBM JESD22-A114E exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
3. Applications
Serial-to-parallel data conversion
Remote control holding register
Nexperia
74LV595
8-bit serial-in/serial-out or parallel-out shift register; 3-state
4. Ordering information
Table 1.
Ordering information
Package
Temperature range
74LV595D
74LV595DB
74LV595PW
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
Name
SO16
SSOP16
TSSOP16
Description
plastic small outline package; 16 leads;
body width 3.9 mm
plastic shrink small outline package; 16 leads;
body width 5.3 mm
Version
SOT109-1
SOT338-1
Type number
plastic thin shrink small outline package; 16 leads; SOT403-1
body width 4.4 mm
5. Functional diagram
Fig 1.
Logic symbol
Fig 2.
Logic symbol (IEEE/IEC)
Fig 3.
Functional diagram
74LV595
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 4 — 18 March 2016
2 of 20
Nexperia
74LV595
8-bit serial-in/serial-out or parallel-out shift register; 3-state
Fig 4.
Logic diagram
Fig 5.
Timing diagram
74LV595
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 4 — 18 March 2016
3 of 20
Nexperia
74LV595
8-bit serial-in/serial-out or parallel-out shift register; 3-state
6. Pinning information
6.1 Pinning
Fig 6.
Pin configuration SO16
Fig 7.
Pin configuration SSOP16, TSSOP16
6.2 Pin description
Table 2.
Symbol
Q0 to Q7
GND
Q7S
MR
SHCP
STCP
OE
DS
V
CC
Pin description
Pin
15, 1, 2, 3, 4, 5, 6, 7
8
9
10
11
12
13
14
16
Description
parallel data output
ground (0 V)
serial data output
master reset (active LOW)
shift register clock input
storage register clock input
output enable input (active LOW)
serial data input
supply voltage
74LV595
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 4 — 18 March 2016
4 of 20
Nexperia
74LV595
8-bit serial-in/serial-out or parallel-out shift register; 3-state
7. Functional description
Table 3.
Input
SHCP STCP OE
X
X
X
X
X
X
L
L
H
L
MR
L
L
L
H
DS
X
X
X
H
Function table
[1]
Output
Q7S
L
L
L
Q6S
Qn
NC
L
Z
NC
a LOW-state on MR only affects the shift register
empty shift register loaded into storage register
shift register clear; parallel outputs in high-impedance OFF-state
logic HIGH-state shifted into shift register stage 0. Contents of all
shift register stages shifted through, e.g. previous state of stage 6
(internal Q6S) appears on the serial output (Q7S).
contents of shift register stages (internal QnS) are transferred to
the storage register and parallel output stages
contents of shift register shifted through; previous contents of the
shift register is transferred to the storage register and the parallel
output stages
Function
X
L
L
H
H
X
X
NC
Q6S
QnS
QnS
[1]
H = HIGH voltage state; L = LOW voltage state;
= LOW-to-HIGH transition; X = don’t care; NC = no change;
Z = high-impedance OFF-state.
8. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
I
OK
I
O
Parameter
supply voltage
input clamping current
output clamping current
output current
V
I
<
0.5
V or V
I
> V
CC
+ 0.5 V
V
I
<
0.5
V or V
I
> V
CC
+ 0.5 V
0.5
V < V
O
< V
CC
+ 0.5 V
standard driver outputs
bus driver outputs
I
CC
I
GND
T
stg
P
tot
supply current
ground current
storage temperature
total power dissipation
T
amb
=
40 C
to +125
C
SO16, SSOP16, TSSOP16
[1]
[2]
[2]
Conditions
Min
0.5
-
-
-
Max
+4.6
20
50
25
35
50
70
Unit
V
mA
mA
mA
mA
mA
mA
mA
mA
standard driver outputs
bus driver outputs
standard driver outputs
bus driver outputs
50
70
65
-
+150
500
C
mW
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For SO16 packages: above 70
C
the value of P
tot
derates linearly with 8 mW/K.
For (T)SSOP16 packages: above 60
C
the value of P
tot
derates linearly with 5.5 mW/K.
74LV595
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 4 — 18 March 2016
5 of 20
微控制器 MCU
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