19-2524; Rev 1; 6/06
Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
General Description
The MAX1190 is a 3.3V, dual 10-bit analog-to-digital con-
verter (ADC) featuring fully differential wideband track-
and-hold (T/H) inputs, driving two ADCs. The MAX1190 is
optimized for low power, small size, and high-dynamic
performance for applications in imaging, instrumentation,
and digital communications. This ADC operates from a
single 3.1V to 3.6V supply, consuming only 492mW while
delivering a typical signal-to-noise and distortion (SINAD)
of 57dB at an input frequency of 60MHz and a sampling
rate of 120Msps. The T/H driven input stages incorporate
400MHz (-3dB) input amplifiers. The converters can also
be operated with single-ended inputs. In addition to low
operating power, the MAX1190 features a 3mA sleep
mode, as well as a 1µA power-down mode to conserve
power during idle periods.
An internal 2.048V precision bandgap reference sets the
full-scale range of the ADC. A flexible reference structure
allows the use of this internal or an externally applied ref-
erence, if desired, for applications requiring increased
accuracy or a different input voltage range.
The MAX1190 features parallel, CMOS-compatible three-
state outputs. The digital output format can be set to two’s
complement or straight offset binary through a single con-
trol pin. The device provides for a separate output power
supply of 1.7V to 3.6V for flexible interfacing with various
logic families. The MAX1190 is available in a 7mm
✕
7mm, 48-pin TQFP-EP package, and is specified for the
extended industrial (-40°C to +85°C) temperature range.
Pin-compatible lower speed versions of the MAX1190 are
also available. Refer to the MAX1180–MAX1184 data
sheets for 105Msps/80Msps/65Msps/40Msps. In addition
to these speed grades, this family includes two multi-
plexed output versions (MAX1185/MAX1186 for
20Msps/40Msps), for which digital data is presented time-
interleaved and on a single, parallel 10-bit output port.
For lower speed, pin-compatible, 8-bit versions of the
MAX1190, refer to the MAX1195–MAX1198 data sheets.
Features
♦
Single 3.3V Operation
♦
Excellent Dynamic Performance
57dB SINAD at f
IN
= 60MHz
64dBc SFDR at f
IN
= 60MHz
♦
-71dBc Interchannel Crosstalk at f
IN
= 60MHz
♦
Low Power
492mW (Normal Operation)
10mW (Sleep Mode)
3.3µW (Shutdown Mode)
♦
0.08dB Gain and 0.8° Phase Matching
♦
Wide ±1V
P-P
Differential Analog Input Voltage
Range
♦
400MHz -3dB Input Bandwidth
♦
On-Chip 2.048V Precision Bandgap Reference
♦
User-Selectable Output Format—Two’s Complement
or Offset Binary
♦
Pin-Compatible, Lower-Speed, 10-Bit and 8-Bit
Versions Available
MAX1190
Ordering Information
PART
MAX1190ECM
TEMP RANGE PIN-PACKAGE PKG CODE
-40°C to +85°C 48 TQFP-EP*
C48E-7
C48E-7
MAX1190ECM+ -40°C to +85°C 48 TQFP-EP*
*EP
= Exposed paddle.
+Denotes
lead-free package.
Pin Configuration
REFN
REFP
REFIN
REFOUT
D9A
D8A
D7A
D6A
D5A
D4A
D3A
D2A
48
47
46
45
44
43
42
41
40
39
38
COM
V
DD
GND
INA+
INA-
V
DD
GND
INB-
INB+
GND
V
DD
CLK
37
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
Applications
Baseband I/Q Sampling
Multichannel IF Sampling
Ultrasound and Medical Imaging
Battery-Powered Instrumentation
WLAN, WWAN, WLL, MMDS Modems
Set-Top Boxes
VSAT Terminals
Functional Diagram appears at end of data sheet.
MAX1190
30
29
28
27
26
25
D1A
D0A
OGND
OV
DD
OV
DD
OGND
D0B
D1B
D2B
D3B
D4B
D5B
EP
13
14
15
16
17
18
19
20
21
22
23
24
TQFP-EP
EP = EXPOSED PADDLE.
NOTE:
THE PIN 1 INDICATOR FOR LEAD-FREE PACKAGES IS REPLACED BY A “+”.
________________________________________________________________
Maxim Integrated Products
GND
V
DD
V
DD
GND
T/B
SLEEP
PD
OE
D9B
D8B
D7B
D6B
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
MAX1190
ABSOLUTE MAXIMUM RATINGS
V
DD
, OV
DD
to GND ...............................................-0.3V to +3.6V
OGND to GND.......................................................-0.3V to +0.3V
INA+, INA-, INB+, INB- to GND ...............................-0.3V to V
DD
REFIN, REFOUT, REFP, REFN, COM,
CLK to GND............................................-0.3V to (V
DD
+ 0.3V)
OE,
PD, SLEEP, T/B,
D9A–D0A, D9B–D0B to OGND ...........-0.3V to (OV
DD
+ 0.3V)
Continuous Power Dissipation (T
A
= +70°C)
48-Pin TQFP-EP (derate 30.4mW/°C above +70°C) ..2430mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
DD
= 3.3V; OV
DD
= 2V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND, REFOUT connected to REFIN through a
10kΩ resistor; V
REFIN
= 2.048V; V
IN
= 2V
P-P
(differential with respect to COM); C
L
= 10pF at digital outputs; f
CLK
= 120MHz; T
A
=
T
MIN
to T
MAX
, unless otherwise noted;
≥
+25°C guaranteed by production test, < +25°C guaranteed by design and characterization;
typical values are at T
A
= +25°C.)
PARAMETER
DC ACCURACY
Resolution
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Gain Error
ANALOG INPUT
Differential Input Voltage Range
Common-Mode Input Voltage
Range
Input Resistance
Input Capacitance
CONVERSION RATE
Maximum Clock Frequency
Data Latency
DYNAMIC CHARACTERISTICS
f
INA or B
= 20.01MHz at -0.5dBFS,
T
A
= +25°C
f
INA or B
= 30.09MHz at -0.5dBFS
f
INA or B
= 59.74MHz at -0.5dBFS
f
INA or B
= 20.01MHz at -0.5dBFS,
T
A
= +25°C
f
INA or B
= 30.09MHz at -0.5dBFS
f
INA or B
= 59.74MHz at -0.5dBFS
54.5
55
58.5
58.2
58
57.5
57
57
dB
dB
f
CLK
120
5
MHz
Clock
Cycles
V
DIFF
V
CM
R
IN
C
IN
Switched capacitor load
Differential or single-ended inputs
±1.0
V
DD
/ 2
±
0.5
20
5
V
V
kΩ
pF
INL
DNL
f
IN
= 7.47MHz
f
IN
= 7.47MHz, no missing codes
guaranteed
-1.0
10
±0.75
±0.4
<
±1
0
±3
+1.5
±1.8
±2
Bits
LSB
LSB
%FS
%FS
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Signal-to-Noise Ratio
SNR
Signal-to-Noise and Distortion
SINAD
2
_______________________________________________________________________________________
Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 3.3V; OV
DD
= 2V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND, REFOUT connected to REFIN through a
10kΩ resistor; V
REFIN
= 2.048V; V
IN
= 2V
P-P
(differential with respect to COM); C
L
= 10pF at digital outputs; f
CLK
= 120MHz; T
A
=
T
MIN
to T
MAX
, unless otherwise noted;
≥
+25°C guaranteed by production test, < +25°C guaranteed by design and characterization;
typical values are at T
A
= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
f
INA or B
= 20.01MHz at -0.5dBFS,
T
A
= +25°C
f
INA or B
= 30.09MHz at -0.5dBFS
f
INA or B
= 59.74MHz at -0.5dBFS
Third-Harmonic
Distortion
f
INA or B
= 20.01MHz at -0.5dBFS,
T
A
= +25°C
f
INA or B
= 30.09MHz at -0.5dBFS
f
INA or B
= 59.74MHz at -0.5dBFS
f
IN1(A or B)
= 43.393MHz at -6.5dBFS,
f
IN2(A or B)
= 48.9017MHz at -6.5dBFS
(Note 1)
f
IN1(A or B)
= 43.393MHz at -6.5dBFS,
f
IN2(A or B)
= 48.9017MHz at -6.5dBFS
(Note 1)
f
INA or B
= 20.01MHz at -0.5dBFS,
T
A
= +25°C
f
INA or B
= 30.09MHz at -0.5dBFS
f
INA or B
= 59.74MHz at -0.5dBFS
Small-Signal Bandwidth
Full-Power Bandwidth
Aperture Delay
Aperture Jitter
Overdrive Recovery Time
INTERNAL REFERENCE
Reference Output Voltage
Load Regulation
Reference Temperature
Coefficient
TC
REF
V
REFOUT
2.048
±3%
1.25
60
V
mV/mA
ppm/°C
FPBW
t
AD
t
AJ
For 1.5× full-scale input
Input at -20dBFS, differential inputs
Input at -0.5dBFS, differential inputs
MIN
58
TYP
67
67
64
-67
-67
-64
-73
dBc
dBc
dBc
MAX
UNITS
MAX1190
Spurious-Free Dynamic Range
SFDR
HD3
Intermodulation Distortion
(First Five Odd-Order IMDs)
Third-Order Intermodulation
Distortion
IMD
IM3
-83
dBc
-65
-65
-63
500
400
1
2
2
-58
dBc
Total Harmonic Distortion
(First Four Harmonics)
THD
MHz
MHz
ns
ps
RMS
ns
BUFFERED EXTERNAL REFERENCE (V
REFIN
= 2.048V)
Positive Reference Output
Voltage
Negative Reference Output
Voltage
Common-Mode Level
Differential Reference Output
Voltage Range
REFIN Resistance
V
REFP
V
REFN
V
COM
ΔV
REF
R
REFIN
(Note 2)
(Note 2)
(Note 2)
ΔV
REF
= V
REFP
- V
REFN
0.95
2.162
1.138
1.651
1.024
> 50
1.09
V
V
V
V
MΩ
_______________________________________________________________________________________
3
Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
MAX1190
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 3.3V; OV
DD
= 2V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND, REFOUT connected to REFIN through a
10kΩ resistor; V
REFIN
= 2.048V; V
IN
= 2V
P-P
(differential with respect to COM); C
L
= 10pF at digital outputs; f
CLK
= 120MHz; T
A
=
T
MIN
to T
MAX
, unless otherwise noted;
≥
+25°C guaranteed by production test, < +25°C guaranteed by design and characterization;
typical values are at T
A
= +25°C.)
PARAMETER
Maximum REFP, COM Source
Current
Maximum REFP, COM Sink
Current
Maximum REFN Source Current
Maximum REFN Sink Current
SYMBOL
I
SOURCE
I
SINK
I
SOURCE
I
SINK
R
REFP
,
R
REFN
ΔV
REF
V
COM
V
REFP
V
REFN
Measured between REFP and COM, and
REFN and COM
ΔV
REF
= V
REFP
- V
REFN
CONDITIONS
MIN
TYP
5
-250
250
-5
MAX
UNITS
mA
µA
µA
mA
UNBUFFERED EXTERNAL REFERENCE (V
REFIN
= AGND, reference voltage applied to REFP, REFN, and COM)
REFP, REFN Input Resistance
Differential Reference Input
Voltage Range
COM Input Voltage Range
REFP Input Voltage
REFN Input Voltage
3.4
1.024
±10%
V
DD
/ 2
±
10%
V
COM
+
ΔV
REF
/ 2
V
COM
-
ΔV
REF
/ 2
0.8
×
V
DD
0.8
×
OV
DD
0.2
×
V
DD
0.2
×
OV
DD
0.1
V
IH
= V
DD
(CLK)
V
IH
= OV
DD
(PD,
OE,
SLEEP, T/B)
V
IL
= 0
5
I
SINK
= -200µA
I
SOURCE
= 200µA
OE
= OV
DD
OE
= OV
DD
3.1
1.7
5
3.3
2.5
3.6
3.6
OV
DD
-
0.2
±10
0.2
±5
±5
±5
pF
V
V
µA
pF
V
V
µA
V
V
V
kΩ
V
V
V
V
DIGITAL INPUTS (CLK, PD,
OE,
SLEEP, T/B)
CLK
Input High Threshold
V
IH
PD,
OE,
SLEEP, T/B
CLK
Input Low Threshold
V
IL
PD,
OE,
SLEEP, T/B
Input Hysteresis
Input Leakage
V
HYST
I
IH
I
IL
Input Capacitance
C
IN
DIGITAL OUTPUTS (D9A–D0A, D9B–D0B)
Output-Voltage Low
V
OL
Output-Voltage High
Three-State Leakage Current
Three-State Output Capacitance
POWER REQUIREMENTS
Analog Supply Voltage Range
Output Supply Voltage Range
V
DD
OV
DD
V
OH
I
LEAK
C
OUT
4
_______________________________________________________________________________________
Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 3.3V; OV
DD
= 2V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND, REFOUT connected to REFIN through a
10kΩ resistor; V
REFIN
= 2.048V; V
IN
= 2V
P-P
(differential with respect to COM); C
L
= 10pF at digital outputs; f
CLK
= 120MHz; T
A
=
T
MIN
to T
MAX
, unless otherwise noted;
≥
+25°C guaranteed by production test, < +25°C guaranteed by design and characterization;
typical values are at T
A
= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
Operating, f
INA and B
= 20.01MHz at
-0.5dBFS
Sleep mode
Shutdown, clock idle, PD =
OE
= OV
DD
Operating, f
INA and B
= 20.01MHz at -0.5dBFS;
see
Typical Operating Characteristics
section, Digital Supply Current vs. Analog
Input Frequency
Sleep mode
Shutdown, clock idle, PD =
OE
= OV
DD
Operating, f
INA and B
= 20.01MHz at
-0.5dBFS
Sleep mode
Shutdown, clock idle, PD =
OE
= OV
DD
Power-Supply Rejection Ratio
TIMING CHARACTERISTICS
CLK Rise to Output Data Valid
Time
OE
Fall to Output Enable Time
OE
Rise to Output Disable Time
CLK Pulse-Width High
PSRR
Offset, V
DD
±5%
Gain, V
DD
±5%
C
L
= 20pF (Note 3)
MIN
TYP
149
3
1
15
µA
MAX
185
UNITS
mA
MAX1190
Analog Supply Current
I
VDD
16
mA
Output Supply Current
I
OVDD
100
2
492
10
3.3
±3.4
±0.81
4.8
4.7
1.2
7.4
50
10
611
µA
Analog Power Dissipation
PDISS
mW
µW
mV/V
%/V
t
DO
t
ENABLE
t
DISABLE
t
CH
ns
ns
ns
ns
CLK Pulse-Width Low
t
CL
Wake-Up Time
t
WAKE
Clock period: 8.34ns; see
Typical Operating
Characteristics
section, AC Performance vs.
Clock Duty Cycle
Clock period: 8.34ns; see
Typical Operating
Characteristics
section, AC Performance vs.
Clock Duty Cycle
Wake up from sleep mode (Note 4)
Wake up from shutdown mode (Note 4)
f
INA or B
= 20.01MHz at -0.5dBFS
f
INA or B
= 20.01MHz at -0.5dBFS (Note 5)
f
INA or B
= 20.01MHz at -0.5dBFS (Note 6)
4.17
4.17
0.65
1.2
-71
0.08
0.8
±0.2
ns
µs
CHANNEL-TO-CHANNEL MATCHING
Crosstalk
Gain Matching
Phase Matching
dBc
dB
Degrees
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Intermodulation distortion is the total power of the intermodulation products relative to the total input power.
REFP, REFN, and COM should be bypassed to GND with a 0.1µF (min) or 1µF (typ) capacitor.
Digital outputs settle to V
IH
, V
IL
. Parameter guaranteed by design.
With REFIN driven externally, REFP, COM, and REFN are left floating while powered down.
Amplitude matching is measured by applying the same signal to each channel and comparing the magnitude of the funda-
mental of the calculated FFT. The data from both ADC channels must be captured simultaneously during this test.
Note 6:
Phase matching is measured by applying the same signal to each channel and comparing the phase of the fundamental of
the calculated FFT. The data from both ADC channels must be captured simultaneously during this test.
_______________________________________________________________________________________
5
NXP MCU
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