Programmable FemtoClock
®
NG LVPECL/LVDS
Clock Generator with 4-Outputs
IDT8T49N004I
DATASHEET
General Description
The IDT8T49N004I is a four output Clock Generator with selectable
LVDS or LVPECL outputs. The IDT8T49N004I can generate any one
of four frequencies from a single crystal or reference clock. The four
frequencies are selected from the Frequency Selection Table (Table
3A) and are programmed via I
2
C interface. The four predefined
frequencies are selected in the user application by two frequency
selection pins. Note the desired programmed frequencies must be
used with the corresponding crystal or clock frequency as indicated
in Table 3A.
Excellent phase noise performance is maintained with IDT’s Fourth
Generation FemtoClock
®
NG PLL technology, which delivers
sub-400fs RMS phase jitter.
Features
•
•
•
•
•
•
•
•
•
•
•
Fourth Generation FemtoClock NG PLL technology
Four selectable LVPECL or LVDS outputs via I
2
C
CLK, nCLK input pair can accept the following differential input
levels: LVPECL, LVDS, HCSL
FemtoClock NG VCO Range: 1.91GHz - 2.5GHz
RMS phase jitter at 156.25MHz (12kHz - 20MHz):
228fs (typical)
RMS phase jitter at 156.25MHz (10kHz - 1MHz): 175fs (typical)
Full 2.5V or 3.3V power supply
I
2
C programming interface
PCI Express (2.5Gb/s), Gen 2 (5Gb/s), and Gen 3 (8Gb/s)
jitter compliant
-40°C to 85°C ambient operating temperature
Lead-free (RoHS 6) packaging
Pin Assignment
V
CCO
nQ2
nQ3
24 23 22 21 20 19 18 17
16
15
14
13
12
11
10
9
1
V
EE
2
Q0
3
nQ0
4
V
CCO
5
Q1
6
nQ1
7
V
EE
8
nc
V
EE
Q2
Q3
FSEL1
V
CC
SCLK
SDATA
V
EE
25
26
27
28
29
30
31
32
V
EE
V
EE
FSEL0
nCLK
CLK
V
EE
XTAL_OUT
XTAL_IN
V
CCA
LOCK
V
EE
V
CC
CLK_SEL
IDT8T49N004I
32-Lead VFQFN
5mm x 5mm x 0.925mm package body
3.15mm x 3.15mm E-Pad
NL Package
IDT8T49N004ANLGI REVISION A OCTOBER 15, 2013
1
©2013 Integrated Device Technology, Inc.
IDT8T49N004I Data Sheet
PROGRAMMABLE FEMTOCLOCK
®
NG LVPECL/LVDS CLOCK GENERATOR WITH 4-OUTPUTS
Block Diagram
IDT8T49N004ANLGI REVISION A OCTOBER 15, 2013
2
©2013 Integrated Device Technology, Inc.
IDT8T49N004I Data Sheet
PROGRAMMABLE FEMTOCLOCK
®
NG LVPECL/LVDS CLOCK GENERATOR WITH 4-OUTPUTS
Table 1. Pin Descriptions
Number
1, 7, 11, 15,
18, 24, 27, 30
2, 3
4, 21
5, 6
8
9,
10
12
13
Name
V
EE
Q0, nQ0
V
CCO
Q1, nQ1
nc
XTAL_IN
XTAL_OUT
CLK
nCLK
Power
Output
Power
Output
Unused
Input
Input
Input
Pulldown
Pullup/
Pulldown
Type
Description
Negative supply pins.
Differential output pair. LVPECL or LVDS interface levels.
Output supply pins.
Differential output pair. LVPECL or LVDS interface levels.
No connect.
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.
Crystal frequency is selected from Table 3A.
Non-inverting differential clock input.
Inverting differential clock input. Internal resistor bias to V
CC
/2.
Frequency and configuration. Selects between one of four factory
programmable power-up default configurations. The four configurations can
have different PLL states, output frequencies, output styles and output
states. These default configurations can be overwritten after power-up via
I
2
C. LVCMOS/LVTTL interface levels.
00 = Configuration 0 (default)
01 = Configuration 1
10 = Configuration 2
11 = Configuration 3
Core supply pins.
Differential output pair. LVPECL or LVDS interface levels.
Differential output pair. LVPECL or LVDS interface levels.
Pullup
Pullup
I
2
C Clock Input. LVCMOS/LVTTL interface levels.
I
2
C Data Input. Input: LVCMOS/LVTTL interface levels.
Output: Open Drain.
Analog supply pin.
PLL Lock Indicator. LVCMOS/LVTTL interface levels.
Pulldown
Input source control pin. LVCMOS/LVTTL interface levels.
0 = XTAL (default)
1 = CLK, nCLK
14, 17
FSEL0,
FSEL1
Input
Pulldown
16, 31
19, 20
22, 23
25
26
28
29
32
V
CC
nQ3, Q3
nQ2, Q2
SCLK
SDATA
V
CCA
LOCK
CLK_SEL
Power
Output
Output
Input
I/O
Power
Output
Input
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLDOWN
R
PULLUP
Parameter
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
Test Conditions
Minimum
Typical
3.5
51
51
Maximum
Units
pF
k
k
IDT8T49N004ANLGI REVISION A OCTOBER 15, 2013
3
©2013 Integrated Device Technology, Inc.
IDT8T49N004I Data Sheet
PROGRAMMABLE FEMTOCLOCK
®
NG LVPECL/LVDS CLOCK GENERATOR WITH 4-OUTPUTS
Frequency Configuration
Table 3A. Frequency Configuration Examples
Output Frequencies
(MHz)
30.72
61.44
62.5
76.8
78.125
100
106.25
122.8
125
133.33
148.5
150
153.6
155.52
Input Frequency or
Crystal Frequency
(MHz)
30.72
30.72
25
30.72
25
25
26.5625
30.72
25
25
27
25
30.72
19.44
25
156.25
100
125
159.375
160
166.66
184.32
61.44
187.5
200
212.5
250
300
25
25
26.5625
25
25
19.44
311.04
77.76
155.52
25
312.5
125
156.25
318.75
Continued on next page.
IDT8T49N004ANLGI REVISION A OCTOBER 15, 2013
4
©2013 Integrated Device Technology, Inc.
26.5625
1
1
1
1
1
1
1
1
2
1
2
5
1
x1
x1
x2
x2
x2
x2
x2
x1
x1
x2
x1
x2
x2
36
90
40
40
40
48
64
32
32
50
40
40
36
12
12
10
10
8
8
8
8
8
8
8
8
6
2211.84
2250
2000
2125
2000
2400
2488.32
2488.32
2488.32
2500
2500
2500
1912.5
26.5625
20
25
30.72
Input Clock
Divider
P
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
5
1
1
1
1
Input Clock
Prescaler
PS
x2
x2
x2
x2
x2
x2
x2
x2
x2
x2
x2
x2
x2
x2
x2
x1
x2
x2
x2
x2
x2
Feedback
Divider
M
32
32
40
40
50
40
40
32
40
48
44
42
40
64
50
50
50
36
48
40
36
Output Divider
N
64
32
32
32
32
20
20
16
16
18
16
14
16
16
16
16
16
12
12
12
12
VCO
Frequency
(MHz)
1966.08
1966.08
2000
2457.6
2500
2000
2125
1966.08
2000
2400
2376
2100
2457.6
2488.32
2500
2500
2500
1912.5
1920
2000
2211.84
IDT8T49N004I Data Sheet
PROGRAMMABLE FEMTOCLOCK
®
NG LVPECL/LVDS CLOCK GENERATOR WITH 4-OUTPUTS
Output Frequencies
(MHz)
322.265625
375
400
425
491.52
Input Frequency or
Crystal Frequency
(MHz)
25.78125
25
25
26.5625
30.72
30.72
Input Clock
Divider
P
2
1
1
1
1
1
2
5
1
1
1
Input Clock
Prescaler
PS
x1
x1
x2
x2
x2
x2
x1
x2
x2
x2
x2
Feedback
Divider
M
150
90
40
40
32
40
40
40
64
50
40
Output Divider
N
6
6
5
5
4
4
4
4
4
4
2
VCO
Frequency
(MHz)
1933.59375
2250
2000
2125
1966.08
2457.6
2457.6
2457.6
2488.32
2500
2457.6
614.4
122.88
153.6
622.08
625
1228.88
19.44
25
30.72
NOTE: Each device supports 4 output frequencies (with related input or crystal value) as selected from this table Register Settings.
NOTE: XTAL operation: f
OUT
= f
REF
* PS * M / N; CLK, nCLK input operation: f
OUT
= (f
REF
/ P) * PS * M / N.
Table 3B. I
2
C Register Map
Binary
Register
Address
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
Register Bit
D7
M0[8]
M1[8]
M2[8]
M3[8]
unused
unused
unused
unused
unused
unused
unused
unused
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
unused
unused
unused
D6
M0[7]
M1[7]
M2[7]
M3[7]
N0[6]
N1[6]
N2[6]
N3[6]
BYPASS0
BYPASS1
BYPASS2
BYPASS3
LVDS_SEL0[Q3]
LVDS_SEL1[Q3]
LVDS_SEL2[Q3]
LVDS_SEL3[Q3]
OE0[Q3]
OE1[Q3]
OE2[Q3]
OE3[Q3]
reserved
unused
unused
unused
D5
M0[6]
M1[6]
M2[6]
M3[6]
N0[5]
N1[5]
N2[5]
N3[5]
PS0[1]
PS1[1]
PS2[1]
PS3[1]
LVDS_SEL0[Q2]
LVDS_SEL1[Q2]
LVDS_SEL2[Q2]
LVDS_SEL3[Q2]
OE0[Q2]
OE1[Q2]
OE2[Q2]
OE3[Q2]
reserved
unused
unused
unused
D4
M0[5]
M1[5]
M2[5]
M3[5]
N0[4]
N1[4]
N2[4]
N3[4]
PS0[0]
PS1[0]
PS2[0]
PS3[0]
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
unused
unused
unused
D3
M0[4]
M1[4]
M2[4]
M3[4]
N0[3]
N1[3]
N2[3]
N3[3]
P0[1]
P1[1]
P2[1]
P3[1]
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
unused
unused
unused
D2
M0[3]
M1[3]
M2[3]
M3[3]
N0[2]
N1[2]
N2[2]
N3[2]
P0[0]
P1[0]
P2[0]
P3[0]
LVDS_SEL0[Q1]
LVDS_SEL1[Q1]
LVDS_SEL2[Q1]
LVDS_SEL3[Q1]
OE0[Q1]
OE1[Q1]
OE2[Q1]
OE3[Q1]
reserved
unused
unused
unused
D1
M0[2]
M1[2]
M2[2]
M3[2]
N0[1]
N1[1]
N2[1]
N3[1]
CP0[1]
CP1[1]
CP2[1]
CP3[1]
LVDS_SEL0[Q0]
LVDS_SEL1[Q0]
LVDS_SEL2[Q0]
LVDS_SEL3[Q0]
OE0[Q0]
OE1[Q0]
OE2[Q0]
OE3[Q0]
unused
unused
unused
unused
D0
M0[1]
M1[1]
M2[1]
M3[1]
N0[0]
N1[0]
N2[0]
N3[0]
CP0[0]
CP1[0]
CP2[0]
CP3[0]
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
unused
unused
unused
unused
Register
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
IDT8T49N004ANLGI REVISION A OCTOBER 15, 2013
5
©2013 Integrated Device Technology, Inc.
电源技术
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
