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74AC540SCX

产品描述buffers & line drivers octal buf/line drv
产品类别逻辑    逻辑   
文件大小94KB,共7页
制造商Fairchild
官网地址http://www.fairchildsemi.com/
标准
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74AC540SCX概述

buffers & line drivers octal buf/line drv

74AC540SCX规格参数

参数名称属性值
Brand NameFairchild Semiconduc
是否无铅不含铅
是否Rohs认证符合
厂商名称Fairchild
零件包装代码SOIC
包装说明SOP, SOP20,.4
针数20
制造商包装代码20LD, SOIC, JEDEC MS013, .300\", WIDE BODY
Reach Compliance Codecompli
ECCN代码EAR99
其他特性WITH DUAL OUTPUT ENABLE
控制类型ENABLE LOW
系列AC
JESD-30 代码R-PDSO-G20
JESD-609代码e3
长度12.8 mm
负载电容(CL)50 pF
逻辑集成电路类型BUS DRIVER
最大I(ol)0.012 A
湿度敏感等级1
位数8
功能数量1
端口数量2
端子数量20
最高工作温度85 °C
最低工作温度-40 °C
输出特性3-STATE
输出极性INVERTED
封装主体材料PLASTIC/EPOXY
封装代码SOP
封装等效代码SOP20,.4
封装形状RECTANGULAR
封装形式SMALL OUTLINE
包装方法TAPE AND REEL
峰值回流温度(摄氏度)260
电源3.3/5 V
Prop。Delay @ Nom-Su8 ns
传播延迟(tpd)7.5 ns
认证状态Not Qualified
座面最大高度2.65 mm
最大供电电压 (Vsup)6 V
最小供电电压 (Vsup)2 V
表面贴装YES
技术CMOS
温度等级INDUSTRIAL
端子面层Matte Tin (Sn)
端子形式GULL WING
端子节距1.27 mm
端子位置DUAL
处于峰值回流温度下的最长时间NOT SPECIFIED
宽度7.5 mm
Base Number Matches1

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74AC540 Octal Buffer/Line Driver with 3-STATE Outputs
November 1988
Revised March 2005
74AC540
Octal Buffer/Line Driver with 3-STATE Outputs
General Description
The AC540 is an octal buffer/line drivers designed to be
employed as memory and address drivers, clock drivers
and bus oriented transmitter/receivers.
These devices are similar in function to the AC240 while
providing flow-through architecture (inputs on opposite side
from outputs). This pinout arrangement makes these
devices especially useful as output ports for microproces-
sors, allowing ease of layout and greater PC board density.
Features
s
I
CC
and I
OZ
reduced by 50%
s
3-STATE inverting outputs
s
Inputs and outputs opposite side of package, allowing
easier interface to microprocessors
s
Output source/sink 24 mA
Ordering Code:
Order Number
74AC540SC
74AC540SJ
74AC540MTC
74AC540PC
Package Number
M20B
M20D
MTC20
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Logic Symbol
IEEE/IEC
Connection Diagram
Truth Table
Inputs
OE
1
L
H
X
L
OE
2
L
X
H
L
I
H
X
X
L
L
Z
Z
H
Outputs
H HIGH Voltage Level
L LOW Voltage Level
X Immaterial
Z High Impedance
FACT
¥
is a trademark of Fairchild Semiconductor Corporation.
© 2005 Fairchild Semiconductor Corporation
Ds009966
www.fairchildsemi.com

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