19-3232; Rev 0; 4/04
KIT
ATION
EVALU
E
BL
AVAILA
Dual, 8-Bit, 165Msps, Current-Output DAC
General Description
The MAX5852 dual, 8-bit, 165Msps digital-to-analog
converter (DAC) provides superior dynamic performance
in wideband communication systems. The device inte-
grates two 8-bit DAC cores, and a 1.24V reference. The
MAX5852 supports single-ended and differential modes
of operation. The dynamic performance is maintained
over the entire 2.7V to 3.6V power-supply operating
range. The analog outputs support a -1.0V to +1.25V
compliance voltage.
The MAX5852 can operate in interleaved data mode to
reduce the I/O pin count. This allows the converter to
be updated on a single, 8-bit bus.
The MAX5852 features digital control of channel gain
matching to within ±0.4dB in sixteen 0.05dB steps.
Channel matching improves sideband suppression in
analog quadrature modulation applications. The on-
chip 1.24V bandgap reference includes a control
amplifier that allows external full-scale adjustments of
both channels through a single resistor. The internal ref-
erence can be disabled and an external reference may
be applied for high-accuracy applications.
The MAX5852 features full-scale current outputs of 2mA
to 20mA and operates from a 2.7V to 3.6V single sup-
ply. The DAC supports three modes of power-control
operation: normal, low-power standby, and complete
power-down. In power-down mode, the operating
current is reduced to 1µA.
The MAX5852 is packaged in a 40-pin thin QFN with
exposed paddle (EP) and is specified for the extended
(-40°C to +85°C) temperature range.
Pin-compatible, lower speed, and higher resolution ver-
sions are also available. Refer to the MAX5853 (10 bit,
80Msps), the MAX5851 (8 bit, 80Msps), and the
MAX5854 (10 bit, 165Msps) data sheets for more infor-
mation. See Table 4.
♦
8-Bit, 165Msps Dual DAC
♦
Low Power
190mW with I
FS
= 20mA at f
CLK
= 165MHz
♦
2.7V to 3.6V Single Supply
♦
Full Output Swing and Dynamic Performance at
2.7V Supply
♦
Superior Dynamic Performance
67dBc SFDR at f
OUT
= 40MHz
♦
Programmable Channel Gain Matching
♦
Integrated 1.24V Low-Noise Bandgap Reference
♦
Single-Resistor Gain Control
♦
Interleaved Data Mode
♦
Single-Ended and Differential Clock Input Modes
♦
Miniature 40-Pin Thin QFN Package, 6mm x 6mm
♦
EV Kit Available—MAX5852 EV Kit
Features
MAX5852
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
40 Thin QFN-EP*
MAX5852ETL
-40°C to +85°C
*EP
= Exposed paddle.
Pin Configuration
OUTNA
OUTNB
OUTPA
OUTPB
TOP VIEW
AGND
AV
DD
AGND
AV
DD
40 39 38 37 36 35 34 33 32 31
REFO
30
CV
DD
29
CGND
28
CLK
27
CV
DD
26
CLKXN
25
CLKXP
24
DCE
23
CW
22
N.C.
21
N.C.
DA7/PD
DA6/DACEN
DA5/IDE
DA4/REN
DA3/G3
DA2/G2
DA1/G1
DA0/G0
N.C.
N.C.
1
2
3
4
5
6
7
8
9
10
11 12 13 14 15 16 17 18 19 20
EP
Applications
Communications
VSAT, LMDS, MMDS, WLAN,
Point-to-Point Microwave Links
Wireless Base Stations
Quadrature Modulation
Direct Digital Synthesis (DDS)
Instrumentation/ATE
MAX5852
DB7
DB5
DB4
DV
DD
DB3
DGND
DB2
DB1
REFR
DB6
THIN QFN
________________________________________________________________
Maxim Integrated Products
DB0
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Dual, 8-Bit, 165Msps, Current-Output DAC
MAX5852
ABSOLUTE MAXIMUM RATINGS
AV
DD
to AGND ...................................................... -0.3V to +4V
DV
DD
to DGND...................................................... -0.3V to +4V
CV
DD
to CGND...................................................... -0.3V to +4V
AV
DD
to DV
DD
.............................................................-4V to +4V
AV
DD
to CV
DD
.............................................................-4V to +4V
DV
DD
to CV
DD
.............................................................-4V to +4V
AGND to DGND.....................................................-0.3V to +0.3V
AGND to CGND.....................................................-0.3V to +0.3V
DGND to CGND ....................................................-0.3V to +0.3V
DA7–DA0, DB7–DB0,
CW, DCE
to DGND ...............-0.3V to +4V
CLK to CGND ..........................................-0.3V to (CV
DD
+ 0.3V)
CLKXN, CLKXP to CGND.........................................-0.3V to +4V
REFR, REFO to AGND .............................-0.3V to (AV
DD
+ 0.3V)
OUTPA, OUTNA to AGND ..........(AV
DD
- 4.8V) to (AV
DD
+ 0.3V)
OUTPB, OUTNB to AGND ..........(AV
DD
- 4.8V) to (AV
DD
+ 0.3V)
Maximum Current into Any Pin
(excluding power supplies) ..........................................±50mA
Continuous Power Dissipation (T
A
= +70°C)
40-Pin QFN (derate 26.3mW/°C above +70°C) .........2105mW
Operating Temperature Range ..........................-40°C to +85°C
Storage Temperature Range ..............................65°C to +150°C
Junction Temperature ......................................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AV
DD
= DV
DD
= CV
DD
= 3V, AGND = DGND = CGND = 0, f
DAC
= 165Msps, differential clock, external reference, V
REF
= 1.2V,
I
FS
= 20mA, output amplitude = 0dB FS, differential output, T
A
= T
MIN
to T
MAX
, unless otherwise noted. T
A
≥
+25°C guaranteed by
production test. T
A
< +25°C guaranteed by design and characterization. Typical values are at T
A
= +25°C.)
PARAMETER
STATIC PERFORMANCE
Resolution
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Gain Error (See Also
Gain Error
Definition
Section)
Gain-Error Temperature Drift
DYNAMIC PERFORMANCE
f
CLK
= 165MHz,
A
OUT
= -1dBFS
Spurious-Free Dynamic Range to
Nyquist
SFDR
f
CLK
= 100MHz,
A
OUT
= -1dBFS
f
CLK
= 25MHz,
A
OUT
= -1dBFS
f
OUT
= 10MHz
f
OUT
= 20MHz
f
OUT
= 40MHz
f
OUT
= 10MHz
f
OUT
= 20MHz
f
OUT
= 30MHz
f
OUT
= 1MHz
64.3
67
66
67
67
67
66
64
68
70
67
63
dBc
dBc
dBc
N
INL
DNL
V
OS
GE
Internal reference (Note1)
External reference
Internal reference
External reference
R
L
= 0
Guaranteed monotonic, R
L
= 0
8
-0.25
-0.15
-0.1
-10
-5.5
±0.05
±0.05
±0.02
±1.5
±0.7
±150
±100
+0.25
+0.15
+0.1
+8
+5.0
Bits
LSB
LSB
LSB
%FSR
ppm/°C
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
f
CLK
= 165MHz, f
OUT
= 10MHz,
A
OUT
= -1dBFS, span = 10MHz
Spurious-Free Dynamic Range
Within a Window
SFDR
f
CLK
= 100MHz, f
OUT
= 5MHz,
A
OUT
= -1dBFS, span = 4MHz
f
CLK
= 25MHz, f
OUT
= 1MHz,
A
OUT
= -1dBFS, span = 2MHz
Multitone Power Ratio to Nyquist
MTPR
8 tones at 400kHz spacing, f
CLK
= 78MHz,
f
OUT
= 15MHz to 18.2MHz
2
_______________________________________________________________________________________
Dual, 8-Bit, 165Msps, Current-Output DAC
ELECTRICAL CHARACTERISTICS (continued)
(AV
DD
= DV
DD
= CV
DD
= 3V, AGND = DGND = CGND = 0, f
DAC
= 165Msps, differential clock, external reference, V
REF
= 1.2V,
I
FS
= 20mA, output amplitude = 0dB FS, differential output, T
A
= T
MIN
to T
MAX
, unless otherwise noted. T
A
≥
+25°C guaranteed by
production test. T
A
< +25°C guaranteed by design and characterization. Typical values are at T
A
= +25°C.)
PARAMETER
Multitone Spurious-Free Dynamic
Range Within a Window
SYMBOL
CONDITIONS
8 tones at 2.1MHz spacing,
f
CLK
= 165MHz, f
OUT
= 28.3MHz to 45.2MHz,
span = 50MHz
f
CLK
= 165MHz,
A
OUT
= -1dBFS
Total Harmonic Distortion to
Nyquist (2nd- Through 8th-Order
Harmonics Included)
THD
f
CLK
= 100MHz,
A
OUT
= -1dBFS
f
CLK
= 25MHz,
A
OUT
= -1dBFS
Output Channel-to-Channel
Isolation
Channel-to-Channel Gain
Mismatch
Channel-to-Channel Phase
Mismatch
f
OUT
= 10MHz
f
OUT
= 10MHz, G[3:0] = 1000
f
OUT
= 10MHz
f
CLK
= 165MHz, f
OUT
= 10MHz, I
FS
= 20mA
Signal-to-Noise Ratio to Nyquist
SNR
f
CLK
= 165MHz, f
OUT
= 10MHz, I
FS
= 5mA
f
CLK
= 65MHz, f
OUT
= 10MHz, I
FS
= 20mA
f
CLK
= 65MHz, f
OUT
= 10MHz, I
FS
= 5mA
Maximum DAC Conversion Rate
Glitch Impulse
Output Settling Time
Output Rise Time
Output Fall Time
ANALOG OUTPUT
Full-Scale Output Current Range
Output Voltage Compliance
Range
Output Leakage Current
REFERENCE
Internal-Reference Output
Voltage
V
REFO
REN
= 0
1.13
1.24
1.32
V
Shutdown or standby mode
I
FS
2
-1.00
-5
20
+1.25
+5
mA
V
µA
t
S
To ±0.1% error band (Note 3)
10% to 90% (Note 3)
90% to 10% (Note 3)
f
DAC
Interleaved mode disabled, IDE = 0
Interleaved mode enabled, IDE = 1
165
82.5
f
OUT
= 10MHz
f
OUT
= 20MHz
f
OUT
= 40MHz
f
OUT
= 10MHz
f
OUT
= 20MHz
f
OUT
= 30MHz
f
OUT
= 1MHz
MIN
TYP
61
-71
-72
-72
-71
-74
-69
-69
90
0.025
0.05
50.5
50.5
51
51
200
100
5
12
2.2
2.2
Msps
pV•s
ns
ns
ns
dB
dB
dB
Degrees
dBc
MAX
UNITS
dBc
MAX5852
_______________________________________________________________________________________
3
Dual, 8-Bit, 165Msps, Current-Output DAC
MAX5852
ELECTRICAL CHARACTERISTICS (continued)
(AV
DD
= DV
DD
= CV
DD
= 3V, AGND = DGND = CGND = 0, f
DAC
= 165Msps, differential clock, external reference, V
REF
= 1.2V,
I
FS
= 20mA, output amplitude = 0dB FS, differential output, T
A
= T
MIN
to T
MAX
, unless otherwise noted. T
A
≥
+25°C guaranteed by
production test. T
A
< +25°C guaranteed by design and characterization. Typical values are at T
A
= +25°C.)
PARAMETER
Internal-Reference Supply
Rejection
Internal-Reference Output-
Voltage Temperature Drift
Internal-Reference Output Drive
Capability
External-Reference Input Voltage
Range
Current Gain
I
FS
/I
REF
0.65 x
DV
DD
0.3 x
DV
DD
-1
3
0.65 x
CV
DD
0.3 x
CV
DD
-1
3
0.9 x
CV
DD
0.1 x
CV
DD
+1
+1
LOGIC INPUTS
(DA7–DA0, DB7–DB0,
CW)
Digital Input-Voltage High
Digital Input-Voltage Low
Digital Input Current
Digital Input Capacitance
V
IH
V
IL
I
IN
C
IN
V
V
µA
pF
TCV
REFO
SYMBOL
CONDITIONS
AV
DD
varied from 2.7V to 3.6V
REN
= 0
REN
= 0
REN
= 1
0.10
MIN
TYP
0.5
±50
50
1.2
32
1.32
MAX
UNITS
mV/V
ppm/°C
µA
V
mA/mA
SINGLE-ENDED CLOCK INPUT/OUTPUT AND
DCE
INPUT
(CLK,
DCE)
Digital Input-Voltage High
Digital Input-Voltage Low
Digital Input Current
Digital Input Capacitance
Digital Output-Voltage High
Digital Output-Voltage Low
V
IH
V
IL
I
IN
C
IN
V
OH
V
OL
DCE
= 1
DCE
= 1
DCE
= 1
DCE
= 1
DCE
= 0, I
SOURCE
= 0.5mA, Figure 1
DCE
= 0, I
SINK
= 0.5mA, Figure 1
V
V
µA
pF
V
V
DIFFERENTIAL CLOCK INPUTS
(CLKXP/CLKXN)
Differential Clock Input Internal
Bias
Differential Clock Input Swing
Clock Input Impedance
POWER REQUIREMENTS
Analog Power-Supply Voltage
Digital Power-Supply Voltage
Clock Power-Supply Voltage
AV
DD
DV
DD
CV
DD
2.7
2.7
2.7
3
3
3
3.6
3.6
3.6
V
V
V
Measured single ended
0.5
5
CV
DD
/2
V
V
kΩ
4
_______________________________________________________________________________________
Dual, 8-Bit, 165Msps, Current-Output DAC
ELECTRICAL CHARACTERISTICS (continued)
(AV
DD
= DV
DD
= CV
DD
= 3V, AGND = DGND = CGND = 0, f
DAC
= 165Msps, differential clock, external reference, V
REF
= 1.2V,
I
FS
= 20mA, output amplitude = 0dB FS, differential output, T
A
= T
MIN
to T
MAX
, unless otherwise noted. T
A
≥
+25°C guaranteed by
production test. T
A
< +25°C guaranteed by design and characterization. Typical values are at T
A
= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
I
FS
= 20mA, single-ended clock mode
Analog Supply Current (Note 2)
I
AVDD
I
FS
= 20mA, differential clock mode
I
FS
= 2mA, single-ended clock mode
I
FS
= 2mA, differential clock mode
Digital Supply Current (Note 2)
I
DVDD
I
FS
= 20mA, single-ended clock mode
I
FS
= 20mA, differential clock mode
Single-ended clock mode (DCE = 1)
Differential clock mode (DCE = 0)
I
AVDD
+ I
DVDD
+ I
CVDD
I
AVDD
+ I
DVDD
+ I
CVDD
Single-ended clock
mode (DCE = 1)
Total Power Dissipation (Note 2)
P
TOT
Differential clock
mode (DCE = 0)
Standby
Shutdown
TIMING CHARACTERISTICS
(Figure 5, Figure 6)
Propagation Delay
DAC Data to CLK Rise/Fall Setup
Time (Note 4)
DAC Data to CLK Rise/Fall Hold
Time (Note 4)
Control Word to
CW
Rise Setup
Time
Control Word to
CW
Rise Hold
Time
CW
High Time
CW
Low Time
DACEN = 1 to V
OUT
Stable Time
(Coming Out of Standby)
t
DCS
t
DCH
t
CS
t
CW
t
CWH
t
CWL
t
STB
Single-ended clock mode (DCE = 1)
Differential clock mode (DCE = 0)
Single-ended clock mode (DCE = 1)
Differential clock mode (DCE = 0)
1.2
2.7
0.8
-0.5
2.5
2.5
5
5
3
1
Clock
cycles
ns
ns
ns
ns
ns
ns
µs
I
FS
= 20mA
I
FS
= 2mA
I
FS
= 20mA
I
FS
= 2mA
MIN
TYP
43.2
43.2
5
5
6
6
13.8
23.7
3.1
1
190
74
219
104
9.3
0.003
11.1
mW
209
3.7
16.5
6.9
mA
MAX
46
mA
UNITS
MAX5852
Clock Supply Current (Note 2)
Total Standby Current
Total Shutdown Current
I
CVDD
I
STANDBY
I
SHDN
mA
mA
µA
_______________________________________________________________________________________
5
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