74VHC574 Octal D-Type Flip-Flop with 3-STATE Outputs
March 1993
Revised May 2005
74VHC574
Octal D-Type Flip-Flop with 3-STATE Outputs
General Description
The VHC574 is an advanced high speed CMOS octal flip-
flop with 3-STATE output fabricated with silicon gate CMOS
technology. It achieves the high speed operation similar to
equivalent Bipolar Schottky TTL while maintaining the
CMOS low power dissipation. This 8-bit D-type flip-flop is
controlled by a clock input (CP) and an output enable input
(OE). When the OE input is HIGH, the eight outputs are in
a high impedance state.
An input protection circuit ensures that 0V to 7V can be
applied to the input pins without regard to the supply volt-
age. This device can be used to interface 5V to 3V systems
and two supply systems such as battery back up. This cir-
cuit prevents device destruction due to mismatched supply
and input voltages.
Features
s
High Speed: t
PD
5.6 ns (typ) at V
CC
V
NIL
5V
s
High Noise Immunity: V
NIH
s
Low Noise: V
OLP
28% V
CC
(Min)
s
Power Down Protection is provided on all inputs
0.6V (typ)
4
P
A (Max) @ T
A
25
q
C
s
Low Power Dissipation: I
CC
s
Pin and Function Compatible with 74HC574
Ordering Code:
Order Number
74VHC574M
74VHC574SJ
74VHC574MTC
74VHC574N
Package Number
M20B
M20D
MTC20
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Logic Symbol
IEEE/IEC
Connection Diagram
Pin Descriptions
Pin Names
D
0
–D
7
CP
OE
O
0
–O
7
Description
Data Inputs
Clock Pulse Input
3-STATE Output Enable Input
3-STATE Outputs
© 2005 Fairchild Semiconductor Corporation
DS011565
www.fairchildsemi.com
74VHC574
Functional Description
The VHC574 consists of eight edge-triggered flip-flops with
individual D-type inputs and 3-STATE true outputs. The
buffered clock and buffered Output Enable are common to
all flip-flops. The eight flip-flops will store the state of their
individual D inputs that meet the setup and hold time
requirements on the LOW-to-HIGH Clock (CP) transition.
With the Output Enable (OE) LOW, the contents of the
eight flip-flops are available at the outputs. When the OE is
HIGH, the outputs go to the high impedance state. Opera-
tion of the OE input does not affect the state of the flip-
flops.
Truth Table
Inputs
D
n
H
L
X
CP
Outputs
OE
L
L
H
O
n
H
L
Z
X
H HIGH Voltage Level
L LOW Voltage Level
X Immaterial
Z High Impedance
LOW-to-HIGH Transition
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.fairchildsemi.com
2
74VHC574
Absolute Maximum Ratings
(Note 1)
Supply Voltage (V
CC
)
DC Input Voltage (V
IN
)
DC Output Voltage (V
OUT
)
Input Diode Current (I
IK
)
Output Diode Current
DC Output Current (I
OUT
)
DC V
CC
/GND Current (I
CC
)
Storage Temperature (T
STG
)
Lead Temperature (T
L
)
(Soldering, 10 seconds)
260
q
C
0.5V to
7.0V
0.5V to
7.0V
0.5V to V
CC
0.5V
20 mA
r
20 mA
r
25 mA
r
75 mA
65
q
C to
150
q
C
Recommended Operating
Conditions
(Note 2)
Supply Voltage (V
CC
)
Input Voltage (V
IN
)
Output Voltage (V
OUT
)
Operating Temperature (T
OPR
)
Input Rise and Fall Time (t
r
, t
f
)
V
CC
V
CC
3.3V
r
0.3V
5.0V
r
0.5V
0
a
100 ns/V
0
a
20 ns/V
2.0V to
5.5V
0V to
5.5V
0V to V
CC
40
q
C to
85
q
C
Note 1:
Absolute Maximum Ratings are values beyond which the device
may be damaged or have its useful life impaired. The databook specifica-
tions should be met, without exception, to ensure that the system design is
reliable over its power supply, temperature, and output/input loading vari-
ables. Fairchild does not recommend operation outside databook specifica-
tions.
Note 2:
Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
OH
Parameter
HIGH Level
Input Voltage
LOW Level
Input Voltage
HIGH Level
Output Voltage
V
CC
(V)
2.0
3.0
5.5
2.0
3.0
5.5
2.0
3.0
4.5
3.0
4.5
V
OL
LOW Level
Output Voltage
2.0
3.0
4.5
3.0
4.5
I
OZ
I
IN
I
CC
3-STATE
Output Off-State Current
Input Leakage
Current
Quiescent Supply
Current
5.5
4.0
40.0
0
5.5
5.5
1.9
2.9
4.4
2.58
3.94
0.0
0.0
0.0
0.1
0.1
0.1
0.36
0.36
2.0
3.0
4.5
T
A
Min
1.50
0.7 V
CC
0.50
0.3 V
CC
1.9
2.9
4.4
2.48
3.80
0.1
0.1
0.1
0.44
0.44
V
I
OL
I
OL
V
IN
V
OUT
V
IN
V
IN
V
IH
or V
IL
V
CC
or GND
5.5V or GND
V
CC
or GND
4 mA
8 mA
V
V
V
IN
or V
IL
V
IH
I
OH
I
OH
I
OL
V
25
q
C
Typ
Max
T
A
40
q
C to
85
q
C
Max
Min
1.50
0.7 V
CC
Units
V
Conditions
0.50
0.3 V
CC
V
V
IN
or V
IL
V
IH
I
OH
50
P
A
4 mA
8 mA
50
P
A
r
0.25
r
0.1
r
2.5
r
1.0
P
A
P
A
P
A
Noise Characteristics
Symbol
V
OLP
(Note 3)
V
OLV
(Note 3)
V
IHD
(Note 3)
V
ILD
(Note 3)
Parameter
Quiet Output Maximum Dynamic V
OL
Quiet Output Minimum Dynamic V
OL
Minimum HIGH Level Dynamic Input Voltage
Maximum LOW Level Dynamic Input Voltage
V
CC
(V)
5.0
5.0
5.0
5.0
T
A
Typ
1.0
25
q
C
Limits
1.2
V
V
V
V
C
L
C
L
C
L
C
L
50 pF
50 pF
50 pF
50 pF
Units
Conditions
0.8
1.0
3.5
1.5
Note 3:
Parameter guaranteed by design.
3
www.fairchildsemi.com
74VHC574
AC Electrical Characteristics
Symbol
t
PLH
t
PHL
Parameter
Propagation Delay
Time (CP to O
n
)
5.0
r
0.5
t
PZL
t
PZH
3-STATE Output
Enable Time
5.0
r
0.5
t
PLZ
t
PHZ
t
OSLH
t
OSHL
f
MAX
3-STATE Output
Disable Time
Output to
Output Skew
Maximum Clock
Frequency
5.0
r
0.5
C
IN
C
OUT
C
PD
Input
Capacitance
Output
Capacitance
Power Dissipation
Capacitance
Note 4:
Parameter guaranteed by design. t
OSLH
|t
PLH max
t
PLH min
|; t
OSHL
|t
PHL max
t
PHL min
|
Note 5:
C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average
operating current can be obtained by the equation: I
CC
(opr.) C
PD
* V
CC
* f
IN
I
CC
/8 (per F/F). The total C
PD
when n pcs. of the Octal D Flip-Flop operates
can be calculated by the equation: C
PD
(total) 20
8n.
V
CC
(V)
3.3
r
0.3
T
A
Min
25
q
C
Typ
8.5
11.0
5.6
7.1
8.2
10.7
5.9
7.4
11.0
7.1
Max
13.2
16.7
8.6
10.6
12.8
16.3
9.0
11.0
15.0
10.1
1.5
1.0
T
A
40
q
C to
85
q
C
Max
15.5
19.0
10.0
12.0
15.0
18.5
10.5
12.5
17.0
11.5
1.5
1.0
65
45
110
75
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Min
Units
ns
ns
ns
ns
ns
ns
R
L
R
L
Conditions
C
L
C
L
C
L
C
L
1 k
:
C
L
C
L
C
L
C
L
1 k
:
C
L
C
L
(Note 4)
C
L
C
L
C
L
C
L
C
L
C
L
V
CC
V
CC
Open
5.0V
15 pF
50 pF
15 pF
50 pF
15 pF
50 pF
15 pF
50 pF
50 pF
50 pF
50 pF
50 pF
15 pF
50 pF
15 pF
50 pF
3.3
r
0.3
3.3
r
0.3
5.0
r
0.5
3.3
r
0.3
5.0
r
0.5
3.3
r
0.3
80
50
130
85
125
75
180
115
4
6
28
10
MHz
10
pF
pF
pF
(Note 5)
AC Operating Requirements
Symbol
t
W
(H)
t
W
(L)
t
S
t
H
Minimum Set-Up Time
Minimum Hold Time
Parameter
Minimum Pulse Width (CP)
V
CC
(V)
3.3
r
0.3
5.0
r
0.5
3.3
r
0.3
5.0
r
0.5
3.3
r
0.3
5.0
r
0.5
T
A
Min
5.0
5.0
3.5
3.5
1.5
1.5
25
q
C
Typ
Max
T
A
40
q
C to
85
q
C
Max
Min
5.0
5.0
3.5
3.5
1.5
1.5
Units
ns
ns
www.fairchildsemi.com
4
74VHC574
Physical Dimensions
inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M20B
5
www.fairchildsemi.com
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
