MCP6N11
500 kHz, 800 µA Instrumentation Amplifier
Features
• Rail-to-Rail Input and Output
• Gain Set by 2 External Resistors
• Minimum Gain (G
MIN
) Options:
1, 2, 5, 10 or 100 V/V
• Common Mode Rejection Ratio (CMRR): 115 dB
(typical, G
MIN
= 100)
• Power Supply Rejection Ratio (PSRR): 112 dB
(typical, G
MIN
= 100)
• Bandwidth: 500 kHz (typical, Gain = G
MIN
)
• Supply Current: 800
μA/channel
(typical)
• Single Channel
• Enable/V
OS
Calibration pin: (EN/CAL)
• Power Supply: 1.8V to 5.5V
• Extended Temperature Range: -40°C to +125°C
Description
Microchip Technology Inc. offers the single MCP6N11
instrumentation amplifier (INA) with Enable/V
OS
Cali-
bration pin (EN/CAL) and several minimum gain
options. It is optimized for single-supply operation with
rail-to-rail input (no common mode crossover distor-
tion) and output performance.
Two external resistors set the gain, minimizing gain
error and drift-over temperature. The reference voltage
(V
REF
) shifts the output voltage (V
OUT
).
The supply voltage range (1.8V to 5.5V) is low enough
to support many portable applications. All devices are
fully specified from -40°C to +125°C.
These parts have five minimum gain options (1, 2, 5, 10
and 100 V/V). This allows the user to optimize the input
offset voltage and input noise for different applications.
Typical Applications
•
•
•
•
High Side Current Sensor
Wheatstone Bridge Sensors
Difference Amplifier with Level Shifting
Power Control Loops
Typical Application Circuit
10
Ω
U
1
MCP6N11
R
F
200 kΩ
R
G
10 kΩ
V
REF
V
OUT
I
DD
V
BAT
+1.8V
to
+5.5V
V
DD
Design Aids
• Microchip Advanced Part Selector (MAPS)
• Demonstration Board
• Application Notes
V
FG
Block Diagram
Package Types
V
OUT
V
OUT
R
F
R
G
V
REF
V
IP
V
IM
V
FG
V
REF
V
IP
V
IM
G
M2
I
2
I
1
G
M1
POR
R
M4
V
DD
V
SS
I
4
Σ
MCP6N11
SOIC
V
FG
1
MCP6N11
2×3 TDFN *
8 EN/CAL
EP
9
7 V
DD
6 V
OUT
5 V
REF
8 EN/CAL V
FG
1
7 V
DD
6 V
OUT
5 V
REF
V
IM
2
V
IP
3
V
SS
4
I
3
G
M3
V
TR
V
IM
2
V
IP
3
V
SS
4
* Includes Exposed Thermal Pad (EP); see
Table 3-1.
Low Power
V
OS
Calibration
EN/CAL
©
2011 Microchip Technology Inc.
DS25073A-page 1
MCP6N11
Minimum Gain Options
Table 1
shows key specifications that differentiate
between the different minimum gain (G
MIN
) options.
See
Section 1.0 “Electrical Characteristics”,
Section 6.0 “Packaging Information”
and
Product
Identification System
for further information on G
MIN
.
TABLE 1:
Part No.
MCP6N11-001
MCP6N11-002
MCP6N11-005
MCP6N11-010
MCP6N11-100
KEY DIFFERENTIATING SPECIFICATIONS
G
MIN
V
OS
∆V
OS
/∆T
A
CMRR (dB) PSRR
(dB)
(V/V) (±mV) (±µV/°C)
Min.
Nom. Max.
Typ.
V
DD
= 5.5V Min.
1
2
5
10
100
3.0
2.0
0.85
0.50
0.35
90
45
18
9.0
2.7
70
78
80
81
88
62
68
75
81
86
V
DMH
(V)
Max.
2.70
1.35
0.54
0.27
0.027
GBWP
(MHz)
Nom.
0.50
1.0
2.5
5.0
35
e
ni
E
ni
(µV
P-P
)
(nV/√Hz)
Nom.
Nom.
(f = 0.1 to 10 Hz) (f = 10 kHz)
570
285
114
57
18
950
475
190
95
35
DS25073A-page 2
©
2011 Microchip Technology Inc.
MCP6N11
1.0
1.1
ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings †
V
DD
– V
SS
.......................................................................6.5V
Current at Input Pins
††
...............................................±2 mA
Analog Inputs (V
IP
and V
IM
)
††
..... V
SS
– 1.0V to V
DD
+ 1.0V
All Other Inputs and Outputs ......... V
SS
– 0.3V to V
DD
+ 0.3V
Difference Input Voltage....................................... |V
DD
– V
SS
|
Output Short Circuit Current ................................ Continuous
Current at Output and Supply Pins ............................±30 mA
Storage Temperature ...................................-65°C to +150°C
Max. Junction Temperature ........................................ +150°C
ESD protection on all pins (HBM, CDM, MM)
.≥
2 kV, 1.5 kV, 300V
† Notice:
Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional
operation of the device at those or any other
conditions above those indicated in the operational
listings of this specification is not implied. Exposure to
maximum rating conditions for extended periods may
affect device reliability.
††
See
Section 4.2.1.2 “Input Voltage Limits”
and
Section 4.2.1.3 “Input Current Limits”.
1.2
Specifications
DC ELECTRICAL SPECIFICATIONS
TABLE 1-1:
Electrical Characteristics:
Unless otherwise indicated, T
A
= +25°C, V
DD
= 1.8V to 5.5V, V
SS
= GND, EN/CAL = V
DD
,
V
CM
= V
DD
/2, V
DM
= 0V, V
REF
= V
DD
/2, V
L
= V
DD
/2, R
L
= 10 kΩ to V
L
and G
DM
= G
MIN
; see
Figure 1-6
and
Figure 1-7.
Parameters
Input Offset
Input Offset Voltage,
Calibrated
Sym
V
OS
Min
-3.0
-2.0
-0.85
-0.50
-0.35
Typ
—
—
—
—
—
0.36
0.21
0.077
0.045
0.014
±90/G
MIN
±2.7
82
88
96
102
112
Max
+3.0
+2.0
+0.85
+0.50
+0.35
—
—
—
—
—
—
—
—
—
—
—
—
Units
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
G
MIN
1
2
5
10
100
1
2
5
10
100
Conditions
(Note
2)
Input Offset Voltage
Trim Step
V
OSTRM
—
—
—
—
—
Input Offset Voltage
Drift
Power Supply
Rejection Ratio
ΔV
OS
/ΔT
A
PSRR
—
—
62
68
75
81
86
µV/°C 1 to 10 T
A
= -40°C to +125°C
(Note
3)
µV/°C
100
dB
dB
dB
dB
dB
1
2
5
10
100
Note 1:
2:
3:
4:
5:
6:
7:
V
CM
= (V
IP
+ V
IM
) / 2, V
DM
= (V
IP
– V
IM
) and G
DM
= 1 + R
F
/R
G
.
The V
OS
spec limits include 1/f noise effects.
This is the input offset drift without V
OS
re-calibration; toggle EN/CAL to minimize this effect.
These specs apply to both the V
IP
, V
IM
input pair (use V
CM
) and to the V
REF
, V
FG
input pair (V
REF
takes V
CM
’s place).
This spec applies to the V
IP
, V
IM
, V
REF
and V
FG
pins individually.
Figure 2-11
and
Figure 2-19
show the V
IVR
and V
DMR
variation over temperature.
See
Section 1.5 “Explanation of DC Error Specs”.
©
2011 Microchip Technology Inc.
DS25073A-page 3
MCP6N11
TABLE 1-1:
DC ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics:
Unless otherwise indicated, T
A
= +25°C, V
DD
= 1.8V to 5.5V, V
SS
= GND, EN/CAL = V
DD
,
V
CM
= V
DD
/2, V
DM
= 0V, V
REF
= V
DD
/2, V
L
= V
DD
/2, R
L
= 10 kΩ to V
L
and G
DM
= G
MIN
; see
Figure 1-6
and
Figure 1-7.
Parameters
Input Bias Current
Across Temperature
Across Temperature
Input Offset Current
Across Temperature
Across Temperature
Common Mode Input
Impedance
Differential Input
Impedance
Input Voltage Range
Common Mode
Rejection Ratio
Sym
I
B
Min
—
—
0
Typ
10
80
2
±1
±5
±0.05
10
13
||6
10
13
||3
Max
—
—
5
—
—
+1
—
—
Units
pA
pA
nA
pA
pA
nA
Ω||pF
Ω||pF
G
MIN
all
Conditions
Input Current and Impedance (Note
4)
T
A
= +85°C
T
A
= +125°C
T
A
= +85°C
T
A
= +125°C
I
OS
—
—
-1
Z
CM
Z
DIFF
—
—
Input Common Mode Voltage (V
CM
or V
REF
) (Note
4)
V
IVL
V
IVH
CMRR
—
V
DD
+ 0.15
62
69
75
79
86
70
78
80
81
88
Common Mode
Non-Linearity
INL
CM
-1000
-570
-230
-125
-50
-400
-220
-100
-50
-30
Note 1:
2:
3:
4:
5:
6:
7:
—
—
79
87
101
107
119
94
100
108
114
115
±115
±27
±11
±6
±2
±42
±10
±4
±2
±1
V
SS
−
0.2
—
—
—
—
—
—
—
—
—
—
—
+1000
+570
+230
+125
+50
+400
+220
+100
+50
+30
V
V
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
ppm
ppm
ppm
ppm
ppm
ppm
ppm
ppm
ppm
ppm
all
1
2
5
10
100
1
2
5
10
100
1
2
5
10
100
1
2
5
10
100
(Note
5, Note 6)
V
CM
= V
IVL
to V
IVH
,
V
DD
= 1.8V
V
CM
= V
IVL
to V
IVH
,
V
DD
= 5.5V
V
CM
= V
IVL
to V
IVH
,
V
DM
= 0V,
V
DD
= 1.8V
(Note
7)
V
CM
= V
IVL
to V
IVH
,
V
DM
= 0V,
V
DD
= 5.5V
(Note
7)
V
CM
= (V
IP
+ V
IM
) / 2, V
DM
= (V
IP
– V
IM
) and G
DM
= 1 + R
F
/R
G
.
The V
OS
spec limits include 1/f noise effects.
This is the input offset drift without V
OS
re-calibration; toggle EN/CAL to minimize this effect.
These specs apply to both the V
IP
, V
IM
input pair (use V
CM
) and to the V
REF
, V
FG
input pair (V
REF
takes V
CM
’s place).
This spec applies to the V
IP
, V
IM
, V
REF
and V
FG
pins individually.
Figure 2-11
and
Figure 2-19
show the V
IVR
and V
DMR
variation over temperature.
See
Section 1.5 “Explanation of DC Error Specs”.
DS25073A-page 4
©
2011 Microchip Technology Inc.
MCP6N11
TABLE 1-1:
DC ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics:
Unless otherwise indicated, T
A
= +25°C, V
DD
= 1.8V to 5.5V, V
SS
= GND, EN/CAL = V
DD
,
V
CM
= V
DD
/2, V
DM
= 0V, V
REF
= V
DD
/2, V
L
= V
DD
/2, R
L
= 10 kΩ to V
L
and G
DM
= G
MIN
; see
Figure 1-6
and
Figure 1-7.
Parameters
Differential Input
Voltage Range
Differential Gain Error
Differential Gain Drift
Differential
Non-Linearity
DC Open-Loop Gain
Sym
V
DML
V
DMH
g
E
Δg
E
/ΔT
A
INL
DM
Min
-2.7/G
MIN
—
-1
—
-500
-800
-2000
Typ
—
—
±0.13
±0.0006
±30
±40
±100
84
90
98
104
116
94
100
108
114
125
—
Max
—
+2.7/G
MIN
+1
—
+500
+800
+2000
—
—
—
—
—
—
—
—
—
—
V
SS
+ 15
Units
V
V
%
%/°C
ppm
ppm
ppm
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
mV
G
MIN
all
Conditions
V
REF
= (V
DD
– G
DM
V
DM
)/2
(Note
6)
V
DM
= V
DML
to V
DMH
,
V
REF
= (V
DD
– G
DM
V
DM
)/2
Input Differential Mode Voltage (V
DM
) (Note
4)
1
2, 5
10, 100
1
2
5
10
100
1
2
5
10
100
all
(Note
7)
A
OL
61
68
76
78
86
70
77
84
90
97
V
DD
= 1.8V,
V
OUT
= 0.2V to 1.6V
V
DD
= 5.5V,
V
OUT
= 0.2V to 5.3V
Output
Minimum Output
Voltage Swing
V
OL
—
V
DM
= -V
DD
/(2G
DM
),
V
DD
= 1.8V,
V
REF
= V
DD
/2 – 1V
V
DM
= -V
DD
/(2G
DM
),
V
DD
= 5.5V,
V
REF
= V
DD
/2 – 1V
V
DM
= V
DD
/(2G
DM
),
V
DD
= 1.8V,
V
REF
= V
DD
/2 + 1V
V
DM
= V
DD
/(2G
DM
),
V
DD
= 5.5V,
V
REF
= V
DD
/2 + 1V
V
DD
= 1.8V
V
DD
= 5.5V
all
I
O
= 0
—
—
V
SS
+ 25
mV
Maximum Output
Voltage Swing
V
OH
V
DD
−
15
—
—
mV
V
DD
−
25
—
—
mV
Output Short Circuit
Current
Power Supply
Supply Voltage
Quiescent Current
per Amplifier
POR Trip Voltage
Note 1:
2:
3:
4:
5:
6:
7:
I
SC
—
—
±8
±30
—
0.8
1.4
1.4
—
—
5.5
1.1
—
1.7
mA
mA
V
mA
V
V
V
DD
I
Q
V
PRL
V
PRH
1.8
0.5
1.1
—
V
CM
= (V
IP
+ V
IM
) / 2, V
DM
= (V
IP
– V
IM
) and G
DM
= 1 + R
F
/R
G
.
The V
OS
spec limits include 1/f noise effects.
This is the input offset drift without V
OS
re-calibration; toggle EN/CAL to minimize this effect.
These specs apply to both the V
IP
, V
IM
input pair (use V
CM
) and to the V
REF
, V
FG
input pair (V
REF
takes V
CM
’s place).
This spec applies to the V
IP
, V
IM
, V
REF
and V
FG
pins individually.
Figure 2-11
and
Figure 2-19
show the V
IVR
and V
DMR
variation over temperature.
See
Section 1.5 “Explanation of DC Error Specs”.
©
2011 Microchip Technology Inc.
DS25073A-page 5
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