Si53365
1:8 L
O W
J
I T T E R
CMOS C
LOCK
B
U FF E R
(<200 MH
Z
)
Features
8 LVCMOS outputs
Ultra-low additive jitter: 150 fs rms
Wide frequency range: 1 to 200 MHz
Asynchronous output enable
Low output-output skew: <150 ps
Low propagation delay variation:
<400 ps
RoHS compliant, Pb-free
Industrial temperature range:
–40 to +85 °C
Footprint-compatible with
CDCLVC1108
1.8, 2.5, or 3.3 V operation
16-TSSOP
Applications
High-speed clock distribution
Ethernet switch/router
Optical Transport Network (OTN)
SONET/SDH
PCI Express Gen 1/2/3
Storage
Telecom
Industrial
Servers
Backplane clock distribution
Ordering Information:
See page 9.
Pin Assignments
Si53365
Q1
16
Q3
15
VDD
14
Q2
13
GND
12
Q5
11
VDD
10
Q7
9
Description
The Si53365 is an ultra low jitter eight output LVCMOS buffer. The Si53365
utilizes Silicon Laboratories' advanced CMOS technology to fanout clocks from 1
MHz to 200 MHz with guaranteed low additive jitter, low skew, and low
propagation delay variability. The Si53365 supports operation over the industrial
temperature range and can be operated from a 1.8 V, 2.5 V, or 3.3 V supply.
Functional Block Diagram
1
CLK
2
OE
3
Q0
4
GND
5
VDD
6
Q4
7
GND
8
Q6
VDD
Power
Supply
Filtering
Q0
Patents pending
Q1
Q2
Q3
CLK
Q4
Q5
Q6
Q7
GND
OE
Preliminary Rev. 0.4 10/12
Copyright © 2012 by Silicon Laboratories
Si53365
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Si53365
T
ABLE O F
C
ONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
2.1. Input Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
2.2. Output Enable Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
2.3. Output Clock Termination Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
2.4. AC Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
3. Pin Description: 16-Pin TSSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
4. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
5. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.1. 16-TSSOP Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
6. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
6.1. 16-TSSOP Package Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
7. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
7.1. Si53365 Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
7.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
2
Preliminary Rev. 0.4
Si53365
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Ambient Operating
Temperature
Supply Voltage Range
Symbol
T
A
V
DD
LVCMOS
Test Condition
Min
–40
1.71
2.38
2.97
Typ
—
1.8
2.5
3.3
Max
85
1.89
2.63
3.63
Unit
°C
V
V
V
Table 2. DC Characteristics
Parameter
Input Voltage
High, CLKn
Input Voltage
Low, CLKn
Input Voltage
High (OE,
CLK_SEL)
Input Voltage
Low (OE,
CLK_SEL)
Output Voltage High
Output Voltage Low
Input Capacitance
Internal Pull up
Resistor
Leakage Current
(V
DD
= 1.8 V
5%,
2.5 V
5%, or 3.3 V
10%,T
A
= –40 to 85
C)
Symbol
V
IH
V
IL
V
IH
Test Condition
Min
V
DD
x
0.7
—
V
DD
x
0.7
—
Typ
—
—
—
Max
—
V
DD
x
0.3
—
Unit
V
V
V
V
IL
—
V
DD
x
0.3
V
V
OH
V
OL
C
IN
R
UP
I
L
I
OH
= –TBD mA
I
OL
= TBD mA
V
DD
x
0.8
V
DD
x
0.2
—
5
25
—
—
TBD
—
—
TBD
TBD
220
V
V
pF
k
A
A
mA
OE, CLK_SEL
Input leakage at all inputs except
CLKn, V
IN
= 0 V
Input leakage at
CLKn, V
IN
= 0 V
—
—
—
—
Operating Supply
Current
I
DD
3.3 V, LVCMOS, C
L
= 5 pF,
200 MHz
Preliminary Rev. 0.4
3
Si53365
Table 3. AC Characteristics
Parameter
Frequency
Duty Cycle
Note:
50% input duty
cycle.
(V
DD
= 1.8 V
5%,
2.5 V
5%, or 3.3 V
10%,T
A
= –40 to 85
C)
Symbol
F
D
C
Test Condition
LVCMOS
200 MHz, 50
toVDD/220/80%
T
R
/T
F
<10% of period
Required to meet prop delay and
additive jitter specifications
(20-80%)
200 MHz, 50
20/80%,
2 pF load, 12 mA drive strength
Min
1
45
Typ
—
—
Max
200
55
Unit
MHz
%
Minimum Input Clock
Slew Rate
Output Rise/Fall Time
SR
0.75
—
—
V/ns
T
R
/T
F
T
W
J
T
PLH,
T
PHL
T
EN
—
—
750
ps
Minimum Input Pulse
Width
Additive Jitter
Propagation Delay
Output Enable Time
500
3.3 V, LVCMOS, 200 MHz,
Vin = 1.2 V
PP
Low to high, high to low
Single-ended
F = 1 MHz
F = 100 MHz
—
TBD
—
—
—
—
—
—
150
—
2
60
2
25
—
—
—
TBD
—
—
—
—
150
ps
fs
ns
s
ns
s
ns
ps
Output Disable Time
T
DIS
F = 1 MHz
F = 100 MHz
Output to Output
Skew
T
SK
Identical Configuration, Single-
ended (Q
N
to Q
M
)
4
Preliminary Rev. 0.4
Si53365
Table 4. Thermal Conditions
Parameter
Thermal Resistance,
Junction to Ambient
Thermal Resistance,
Junction to Case
Symbol
Test Condition
Still air
Still air
Value
102.42
32.62
Unit
°C/W
°C/W
JA
JC
Table 5. Absolute Maximum Ratings
Parameter
Storage Temperature
Supply Voltage
Input Voltage
Output Voltage
ESD Sensitivity
ESD Sensitivity
Peak Soldering Reflow
Temperature
Maximum Junction
Temperature
Symbol
T
S
VDD
V
IN
V
OUT
HBM
CDM
T
PEAK
T
J
Pb-Free; Solder reflow profile per
JEDEC J-STD-020
HBM, 100 pF, 1.5 kΩ
Test Condition
Min
–55
–0.5
–0.5
—
2000
500
—
—
Typ
—
—
—
—
—
—
—
—
Max
150
3.8
VDD+
0.3
VDD+
0.3
—
—
260
125
Unit
C
V
V
V
V
V
C
C
Note:
Stresses beyond those listed in this table may cause permanent damage to the device. Functional operation
specification compliance is not implied at these conditions. Exposure to maximum rating conditions for extended
periods may affect device reliability.
Preliminary Rev. 0.4
5
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