S i 5 3 4 7 /4 6
D
UAL
/ Q
UAD
D S P L L A
N Y
- F
R E Q U E N C Y
, A
NY
-O
U TP U T
J
ITTER
A
TTENUATORS
Features
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
IN1
IN1
LOL_A
LOL_B
LOL_C
RST
X1
XA
XB
X2
OE0
INTR
VDDA
IN2
IN2
SCLK
49
Four or two independent DSPLLs in
a single monolithic IC
Each DSPLL generates any output
frequency from any input frequency
Input frequency range:
Differential: 8 kHz to 750 MHz
LVCMOS: 8 kHz to 250 MHz
Output frequency range:
Differential: up to 800 MHz
LVCMOS: up to 250 MHz
Jitter performance:
<100 fs typ (12 kHz–20 MHz)
Flexible crosspoints route any input
to any output clock
Programmable jitter attenuation
bandwidth per DSPLL: 0.1 Hz to
4 kHz
Highly configurable outputs
compatible with LVDS, LVPECL,
LVCMOS, programmable signal
swings
Status monitoring (LOS, OOF, LOL)
Hitless input clock switching:
automatic or manual
Locks to gapped clock inputs
Automatic free-run and holdover
modes
Fastlock: <200 ms lock time
Glitchless on-the-fly DSPLL
frequency changes
DCO mode: as low as 0.01 ppb
steps per DSPLL
Core voltage:
V
DD
: 1.8 V ±5%
V
DDA
:
3.3 V ±5%
Ordering Information:
See section 7
Independent output supply pins:
3.3V, 2.5V, or 1.8V
Output-output skew:
<100 ps per DSPLL
Pin Assignments
Si5347 64QFN
Top View
VDDO7
VDDO6
VDDO5
RSVD
RSVD
OUT7
OUT7
OUT6
OUT6
OUT5
OUT5
VDD
IN0
IN0
IN3
IN3
Serial interface: I
2
C or SPI
In-circuit programmable with non-
volatile OTP memory
ClockBuilder Pro software tool
simplifies device configuration
Si5347: Quad DSPLL, 4 input,
8 output, 64 QFN
Si5346: Dual DSPLL, 4 input,
4 output, 44 QFN
Temperature range: –40 to +85 °C
Pb-free, RoHS-6 compliant
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
48
47
46
45
44
43
42
FINC
LOL_D
VDD
OUT4
OUT4
VDDO4
FDEC
OE1
VDDS
I2C_SEL
OUT3
OUT3
VDDO3
OUT2
OUT2
VDDO2
GND
Pad
41
40
39
38
37
36
35
34
33
Applications
A1/SDO
OUT0
OUT0
OUT1
34
VDDO0
DSPLL_SEL0
DSPLL_SEL1
LOS_XAXB
SDA/SDIO
VDDO1
A0/CS
RSVD
RSVD
OUT1
NC
I2C_SEL
Description
The Si5347 is a high performance jitter attenuating clock multiplier which
integrates four any-frequency DSPLLs for applications that require maximum
integration and independent timing paths. The Si5346 is a dual DSPLL version in
a smaller package. Each DSPLL has access to any of the four inputs and can
provides low jitter clocks on any of the device outputs. Based on 4
th
generation
DSPLL technology, these devices provide any-frequency conversion with typical
jitter performance of 100 fs. Each DSPLL supports independent free-run,
holdover modes of operation, and offers automatic and hitless input clock
switching. The Si5347/46 is programmable via a serial interface with in-circuit
programmable non-volatile memory so that it always powers up with a known
configuration. Programming the Si5347/46 is made easy with Silicon Labs’
ClockBuilderPro
software. Factory pre-programmed devices are also available.
IN1
IN1
RST
X1
XA
XB
X2
VDDA
VDDA
IN2
IN2
1
2
3
4
5
6
7
8
9
10
11
44
43
42
41
40
39
38
37
36
35
VDDO3
33
32
31
30
29
OTN Muxponders and
Carrier Ethernet switches
Transponders
Broadcast video
10/40/100G network line cards
GbE/10GbE/100GbE Synchronous
Ethernet
Si5346 44QFN
Top View
OE1
OUT3
OUT3
IN3
VDD
IN0
IN0
IN3
VDD
VDD
LOS_XAXB
VDD
OUT2
OUT2
VDDO2
LOL_A
LOL_B
VDDS
OUT1
OUT1
VDDO1
GND
Pad
28
27
26
25
24
23
12
13
14
15
16
17
18
19
20
21
A0/CS
OE0
SDA/SDIO
A1/SDO
VDDO0
Preliminary Rev. 0.9 7/14
Copyright © 2014 by Silicon Laboratories
OUT0
VDD
SCLK
INTR
OUT0
NC
22
Si5347/46
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Si5347/46
Functional Block Diagram
XTAL/
REFCLK
Si5347/46
XA
OSC
XB
÷INT
÷INT
÷INT
÷INT
÷INT
÷INT
IN3
÷FRAC
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
IN0
÷FRAC
DSPLL
A
DSPLL
B
DSPLL
C
DSPLL
D
Si5346
IN1
÷FRAC
IN2
÷FRAC
÷INT
÷INT
Si5347
NVM
I
2
C/SPI
Control/
Status
OUT7
2
Preliminary Rev. 0.9
Si5347/46
T
ABLE
O
F
C
ON TENTS
1. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
3. Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.1. Frequency Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.2. DSPLL Loop Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.3. Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.4. Digitally-Controlled Oscillator (DCO) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.5. External Reference (XA/XB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.6. Inputs (IN0, IN1, IN2, IN3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.7. Fault Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
4.8. Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
4.9. Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.10. In-Circuit Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.11. Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
4.12. Custom Factory Preprogrammed Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.1. Addressing Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8. Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
8.1. Si5347 9x9 mm 64-QFN Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
8.2. Si5346 7x7 mm 44-QFN Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
9. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
10. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
11. Device Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Appendix—Advance Product Information Revision History . . . . . . . . . . . . . . . . . . . . . . . 51
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Preliminary Rev. 0.9
3
Si5347/46
1. Typical Application Schematic
OTN Muxponder
Client #1
Data
PHY
Clock
PD
÷
LPF
M
n_A
M
d_A
DSPLL A
Client #2
Data
PHY
Clock
PD
÷
LPF
M
n_B
M
d_B
DSPLL B
Si5347
10GbE
Gapped Clock
Non-gapped
Jitter Attenuated Clock
10GbE
40G OTN
Gapped Clock
OTN
De-Mapper
Client #3
Data
Non-gapped
Jitter Attenuated Clock
PHY
Clock
PD
Gapped Clock
÷
LPF
M
n_C
M
d_C
DSPLL C
Client #4
Data
PHY
Clock
PD
÷
LPF
M
n_D
M
d_D
DSPLL D
Non-gapped
Jitter Attenuated Clock
10GbE
10GbE
Gapped Clock
Non-gapped
Jitter Attenuated Clock
Figure 1. Using The Si5347 to Clean Gapped Clocks in an OTN Application
4
Preliminary Rev. 0.9
Si5347/46
2. Electrical Specifications
Table 1. Recommended Operating Conditions
(V
DD
= 1.8 V ±5%, V
DDA
= 3.3 V ±5%,T
A
= –40 to 85 °C)
Parameter
Ambient Temperature
Junction Temperature
Core Supply Voltage
Output Driver Supply Voltage
Symbol
T
A
TJ
MAX
V
DD
V
DDA
V
DDO
Min
–40
—
1.71
3.14
3.14
2.38
1.71
Typ
25
—
1.80
3.30
3.30
2.50
1.80
3.30
1.80
Max
85
125
1.89
3.47
3.47
2.62
1.89
3.47
1.89
Units
°C
°C
V
V
V
V
V
V
V
Status Pin Supply Voltage
V
DDS
3.14
1.71
Note:
All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted.
Table 2. DC Characteristics
(V
DD
= 1.8 V ±5%, V
DDA
= 3.3 V ±5%, V
DDO
= 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, T
A
= –40 to 85 °C)
Parameter
Core Supply Current
Symbol
I
DD
Test Condition
Si5347
Si5346
Notes
1
,
2
Min
—
—
—
Typ
270
—
125
Max
365
173
137
Units
mA
mA
mA
I
DDA
Note:
1.
2.
3.
4.
Si5347
Si5347 test configuration: 7 x 2.5 V LVDS outputs enabled @156.25 MHz. Excludes power in termination resistors.
Si5346 test configuration: 4 x 2.5 V LVDS outputs enabled @ 156.25 MHz. Excludes power in termination resistors.
Differential outputs terminated into an AC coupled 100
load.
LVCMOS outputs measured into a 6 inch 50
PCB trace with 5 pF load.
Differential Output Test Configuration
I
DDO
OUT
OUT
50
50
100
I
DDO
OUTa
OUTb
LVCMOS Output Test Configuration
6 inch
50
5 pF
5.
Detailed power consumption for any configuration can be estimated using
ClockBuilderPro
when an evaluation board
(EVB) is not available. All EVBs support detailed current measurements for any configuration.
Preliminary Rev. 0.9
5
FPGA/CPLD
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