19-3063; Rev 0; 1/04
Ultra-Low-Power, 12-Bit,
Voltage-Output DACs
General Description
The MAX5530/MAX5531 are single, 12-bit, ultra-low-
power, voltage-output, digital-to-analog converters
(DACs) offering Rail-to-Rail
®
buffered voltage outputs.
The DACs operate from a 1.8V to 5.5V supply and con-
sume less than 6µA, making them desirable for low-
power and low-voltage applications. A shutdown mode
reduces overall current, including the reference input
current, to just 0.18µA. The MAX5530/MAX5531 use a
3-wire serial interface that is compatible with SPI™,
QSPI™, and MICROWIRE™.
At power-up, the MAX5530/MAX5531 outputs are driven
to zero scale, providing additional safety for applications
that drive valves or for other transducers that must be off
during power-up. The zero-scale outputs enable glitch-
free power-up.
The MAX5530 accepts an external reference input. The
MAX5531 contains an internal reference and provides
an external reference output. Both devices have force-
sense-configured output buffers.
The MAX5530/MAX5531 are available in a 4mm x 4mm x
0.8mm, 12-pin, thin QFN package and are guaranteed
over the extended -40°C to +85°C temperature range.
For 10-bit compatible devices, refer to the MAX5520/
MAX5521 data sheet. For 8-bit compatible devices,
refer to the MAX5510/MAX5511 data sheet.
♦
Ultra-Low 6µA Supply Current
♦
Shutdown Mode Reduces Supply Current to
0.18µA (max)
♦
Single +1.8V to +5.5V Supply
♦
Small 4mm x 4mm x 0.8mm Thin QFN Package
♦
Flexible Force-Sense-Configured Rail-to-Rail
Output Buffers
♦
Internal Reference Sources 8mA of Current
(MAX5531)
♦
Fast 16MHz 3-Wire SPI-/QSPI-/MICROWIRE-
Compatible Serial Interface
♦
TTL- and CMOS-Compatible Digital Inputs with
Hysteresis
♦
Glitch-Free Outputs During Power-Up
Features
MAX5530/MAX5531
Ordering Information
PART
MAX5530ETC
MAX5531ETC
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
12 Thin QFN-EP*
12 Thin QFN-EP*
*EP
= Exposed paddle (internally connected to GND).
Applications
Portable Battery-Powered Devices
Instrumentation
Automatic Trimming and Calibration in Factory
or Field
Programmable Voltage and Current Sources
Industrial Process Control and Remote
Industrial Devices
Remote Data Conversion and Monitoring
Chemical Sensor Cell Bias for Gas Monitors
Programmable Liquid Crystal Display (LCD) Bias
4
5
DIN
3
CS
SCLK
1
2
Pin Configuration
TOP VIEW
FB
12
N.C.
11
OUT
10
9
8
7
GND
V
DD
N.C.
MAX5530
MAX5531
6
N.C.
Selector Guide
PART
MAX5530ETC
MAX5531ETC
REFERENCE
External
Internal
TOP MARK
AACS
AACT
REFIN (MAX5530) N.C.
REFOUT(MAX5531)
THIN QFN
Rail-to-Rail is a registered trademark of Nippon Motorola, Inc.
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Ultra-Low-Power, 12-Bit,
Voltage-Output DACs
MAX5530/MAX5531
ABSOLUTE MAXIMUM RATINGS
V
DD
to GND ..............................................................-0.3V to +6V
OUT to GND ...............................................-0.3V to (V
DD
+ 0.3V)
FB to GND ..................................................-0.3V to (V
DD
+ 0.3V)
SCLK, DIN,
CS
to GND ..............................-0.3V to (V
DD
+ 0.3V)
REFIN, REFOUT to GND ............................-0.3V to (V
DD
+ 0.3V)
Continuous Power Dissipation (T
A
= +70°C)
Thin QFN (derate 16.9mW/°C above +70°C ..............1349mW
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Junction Temperature ..................................................... +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
DD
= +1.8V to +5.5V, OUT unloaded, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
12
±4
±4
±0.2
±0.2
±1
±1
±2
GE
V
DD
= 5V, V
REF
= 4.096V
V
DD
= 1.8V, V
REF
= 1.024V
±2
±2
±4
PSRR
N
INL
V
DD
= 5V, V
REF
= 3.9V
V
DD
= 1.8V, V
REF
= 1.2V
Guaranteed monotonic,
V
DD
= 5V, V
REF
= 3.9V
Guaranteed monotonic,
V
DD
= 1.8V, V
REF
= 1.2V
Offset Error (Note 2)
Offset-Error Temperature Drift
Gain Error (Note 3)
Gain-Error Temperature
Coefficient
GE
V
DD
= 5V, V
REF
= 3.9V
V
DD
= 1.8V, V
REF
= 1.2V
V
OS
V
DD
= 5V, V
REF
= 3.9V
V
DD
= 1.8V, V
REF
= 1.2V
1.8V
≤
V
DD
≤
5.5V
12
±4
±4
±0.2
±0.2
±1
±1
±2
±2
±2
±4
±4
±4
±8
±8
±1
LSB
±1
±20
±20
mV
µV/°C
LSB
ppm/°C
85
±4
±4
±8
±8
±1
LSB
±1
±20
±20
mV
µV/°C
LSB
ppm/°C
dB
Bits
LSB
TYP
MAX
UNITS
Bits
LSB
STATIC ACCURACY (MAX5530 EXTERNAL REFERENCE)
Resolution
N
Integral Nonlinearity (Note 1)
INL
V
DD
= 5V, V
REF
= 4.096V
V
DD
= 1.8V, V
REF
= 1.024V
Guaranteed monotonic,
V
DD
= 5V, V
REF
= 4.096V
Guaranteed monotonic,
V
DD
= 1.8V, V
REF
= 1.024V
Offset Error (Note 2)
Offset-Error Temperature Drift
Gain Error (Note 3)
Gain-Error Temperature
Coefficient
Power-Supply Rejection Ratio
Resolution
Integral Nonlinearity (Note 1)
STATIC ACCURACY (MAX5531 INTERNAL REFERENCE)
V
OS
V
DD
= 5V, V
REF
= 4.096V
V
DD
= 1.8V, V
REF
= 1.024V
Differential Nonlinearity (Note 1)
DNL
Differential Nonlinearity (Note 1)
DNL
2
_______________________________________________________________________________________
Ultra-Low-Power, 12-Bit,
Voltage-Output DACs
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= +1.8V to +5.5V, OUT unloaded, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.)
PARAMETER
Power-Supply Rejection Ratio
REFERENCE INPUT (MAX5530)
Reference-Input Voltage Range
Reference-Input Impedance
REFERENCE OUTPUT (MAX5531)
No external load, V
DD
= 1.8V
Initial Accuracy
V
REFOUT
No external load, V
DD
= 2.5V
No external load, V
DD
= 3V
No external load, V
DD
= 5V
Output-Voltage Temperature
Coefficient
Line Regulation
V
TEMPCO
T
A
= -40°C to +85°C (Note 4)
V
REFOUT
< V
DD
- 200mV (Note 5)
0
≤
I
REFOUT
≤
1mA, sourcing, V
DD
= 1.8V,
V
REF
= 1.2V
Load Regulation
0
≤
I
REFOUT
≤
8mA, sourcing, V
DD
= 5V,
V
REF
= 3.9V
-150µA
≤
I
REFOUT
≤
0, sinking
0.1Hz to 10Hz, V
REFOUT
= 3.9V
Output Noise Voltage
10Hz to 10kHz, V
REFOUT
= 3.9V
0.1Hz to 10Hz, V
REFOUT
= 1.2V
10Hz to 10kHz, V
REFOUT
= 1.2V
Short-Circuit Current (Note 6)
Capacitive Load Stability Range
Thermal Hysteresis
Reference Power-Up Time (from
Shutdown)
Long-Term Stability
DAC OUTPUT (OUT)
Capacitive Driving Capability
C
L
V
DD
= 5V, V
OUT
set to full scale, OUT
shorted to GND, source current
V
DD
= 5V, V
OUT
set to 0V, OUT shorted to
V
DD
, sink current
V
DD
= 1.8V, V
OUT
set to full scale, OUT
shorted to GND, source current
V
DD
= 1.8V, V
OUT
set to 0V, OUT shorted to
V
DD
, sink current
1000
65
65
mA
14
14
pF
V
DD
= 5V
V
DD
= 1.8V
(Note 7)
(Note 8)
REFOUT unloaded, V
DD
= 5V
REFOUT unloaded, V
DD
= 1.8V
1.197
1.913
2.391
3.828
1.214
1.940
2.425
3.885
12
2
0.3
0.3
0.2
150
600
50
450
30
14
0 to 10
200
5.4
4.4
200
mA
nF
ppm
ms
ppm/
1khrs
µV
P-P
1.231
1.967
2.459
3.941
30
200
2
2
µV/µA
ppm/°C
µV/V
V
V
REFIN
R
REFIN
Normal operation
In shutdown
0
4.1
2.5
V
DD
V
MΩ
GΩ
SYMBOL
PSRR
CONDITIONS
1.8V
≤
V
DD
≤
5.5V
MIN
TYP
85
MAX
UNITS
dB
MAX5530/MAX5531
Short-Circuit Current (Note 6)
_______________________________________________________________________________________
3
Ultra-Low-Power, 12-Bit,
Voltage-Output DACs
MAX5530/MAX5531
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= +1.8V to +5.5V, OUT unloaded, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
Coming out of shutdown
(MAX5530)
DAC Power-Up Time
Coming out of standby
(MAX5531)
Output Power-Up Glitch
FB_ Input Current
DIGITAL INPUTS (SCLK, DIN,
CS)
4.5V
≤
V
DD
≤
5.5V
Input High Voltage
V
IH
2.7V
<
V
DD
≤
3.6V
1.8V
≤
V
DD
≤
2.7V
Input Low Voltage
Input Leakage Current
Input Capacitance
DYNAMIC PERFORMANCE
Voltage-Output Slew Rate
Voltage-Output Settling Time
SR
Positive and negative (Note 10)
0.1 to 0.9 of full scale to within 0.5 LSB
(Note 10)
0.1Hz to 10Hz
Output Noise Voltage
10Hz to 10kHz
POWER REQUIREMENTS
Supply Voltage Range
V
DD
V
DD
= 5V
MAX5530
Supply Current (Note 9)
I
DD
MAX5531
V
DD
= 3V
V
DD
= 1.8V
V
DD
= 5V
V
DD
= 3V
V
DD
= 1.8V
V
DD
= 5V
Standby Supply Current
Shutdown Supply Current
I
DDSD
I
DDPD
(Note 9)
(Note 9)
V
DD
= 3V
V
DD
= 1.8V
1.8
2.6
2.6
3.6
5.3
4.8
5.4
3.3
2.8
2.4
0.05
5.5
4
4
5
7.0
7.0
7.0
4.5
4.0
3.5
0.25
µA
µA
µA
V
V
DD
= 5V
V
DD
= 1.8V
V
DD
= 5V
V
DD
= 1.8V
10
660
80
55
620
476
µV
P-P
V/ms
µs
V
IL
I
IN
C
IN
4.5V
≤
V
DD
≤
5.5V
2.7V
<
V
DD
≤
3.6V
1.8V
≤
V
DD
≤
2.7V
(Note 9)
±0.05
10
2.4
2.0
0.7 x V
DD
0.8
0.6
0.3 x V
DD
±0.5
V
µA
pF
V
C
L
= 100pF
V
DD
= 5V
V
DD
= 1.8V
V
DD
= 1.8V
to 5.5V
MIN
TYP
3
3.8
0.4
10
10
mV
pA
ms
MAX
UNITS
4
_______________________________________________________________________________________
Ultra-Low-Power, 12-Bit,
Voltage-Output DACs
TIMING CHARACTERISTICS
(V
DD
= +4.5V to +5.5V, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.)
PARAMETER
Serial Clock Frequency
DIN to SCLK Rise Setup Time
DIN to SCLK Rise Hold Time
SCLK Pulse-Width High
SCLK Pulse-Width Low
CS
Pulse-Width High
SCLK Rise to
CS
Rise Hold Time
CS
Fall to SCLK Rise Setup Time
SCLK Fall to
CS
Fall Setup
CS
Rise to SCK Rise Hold Time
SYMBOL
f
SCLK
t
DS
t
DH
t
CH
t
CL
t
CSW
t
CSH
t
CSS
t
CSO
t
CS1
CONDITIONS
MIN
0
15
0
24
24
100
0
20
0
20
TYP
MAX
16.7
UNITS
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
MAX5530/MAX5531
TIMING CHARACTERISTICS (V
DD
= 4.5V TO 5.5V)
TIMING CHARACTERISTICS
(V
DD
= +1.8V to +5.5V, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.)
PARAMETER
Serial Clock Frequency
DIN to SCLK Rise Setup Time
DIN to SCLK Rise Hold Time
SCLK Pulse-Width High
SCLK Pulse-Width Low
CS
Pulse-Width High
SCLK Rise to
CS
Rise Hold Time
CS
Fall to SCLK Rise Setup Time
SCLK Fall to
CS
Fall Setup
CS
Rise to SCK Rise Hold Time
SYMBOL
f
SCLK
t
DS
t
DH
t
CH
t
CL
t
CSW
t
CSH
t
CSS
t
CSO
t
CS1
CONDITIONS
MIN
0
24
0
40
40
150
0
30
0
30
TYP
MAX
10
UNITS
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
TIMING CHARACTERISTICS (V
DD
= 1.8V TO 5.5V)
Note 1:
Linearity is tested within codes 96 to 4080.
Note 2:
Offset is tested at code 96.
Note 3:
Gain is tested at code 4095. FB is connected to OUT.
Note 4:
Guaranteed by design. Not production tested.
Note 5:
V
DD
must be a minimum of 1.8V.
Note 6:
Outputs can be shorted to V
DD
or GND indefinitely, provided that the package power dissipation is not exceeded.
Note 7:
Optimal noise performance is at 2nF load capacitance.
Note 8:
Thermal hysteresis is defined as the change in the initial +25°C output voltage after cycling the device from T
MAX
to T
MIN
.
Note 9:
All digital inputs at V
DD
or GND.
Note 10:
Load = 10kΩ in parallel with 100pF, V
DD
= 5V, V
REF
= 4.096V (MAX5530) or V
REF
= 3.9V (MAX5531).
_______________________________________________________________________________________
5
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