Low Skew, 1-to-9
LVCMOS/LVTTL Fanout Buffer
83947I-147
Data Sheet
G
ENERAL
D
ESCRIPTION
The 83947I-147 is a low skew, 1-to-9 LVCMOS/LVTTL
Fanout Buffer. The low impedance LVCMOS/LVTTL outputs
are designed to drive 50 series or parallel terminated
transmission lines. The effective fanout can be increased from
9 to 18 by utilizing the ability of the outputs to drive two series
terminated lines.
Guaranteed output and part-to-part skew characteristics make
the 83947I-147 ideal for high performance, 3.3V or 2.5V single
ended applications.
F
EATURES
•
Nine LVCMOS/LVTTL outputs
•
Selectable CLK0 and CLK1 can accept the following
input levels: LVCMOS and LVTTL
•
Maximum output frequency: 250MHz
•
Output skew: 115ps (maximum)
•
Part-to-part skew: 500ps (maximum)
•
Additive phase jitter, RMS: 0.02ps (typical) @ 3.3V
•
Full 3.3V or 2.5V operating supply
•
-40°C to 85°C ambient operating temperature
•
Lead-free (RoHS 6) packaging
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
V
DDO
V
DDO
GND
GND
GND
Q0
Q1
Q2
32 31 30 29 28 27 26 25
GND
CLK_SEL
CLK0
CLK1
CLK_EN
OE
V
DD
GND
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
GND
V
DDO
Q8
GND
Q7
V
DDO
Q6
GND
24
23
22
GND
Q3
V
DDO
Q4
GND
Q5
V
DDO
GND
ICS83947I-147
21
20
19
18
17
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
©2016 Integrated Device Technology, Inc
1
Revision A March 18, 2016
83947I-147 Data Sheet
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 8, 9, 12, 16, 17, 20,
24, 25, 29, 32
2
3, 4
5
6
7
Name
GND
CLK_SEL
CLK0, CLK1
CLK_EN
OE
V
DD
Type
Power
Input
Input
Input
Input
Power
Pullup
Power supply ground.
Clock select input. When HIGH, selects CLK1. When LOW,
selects CLK0. LVCMOS / LVTTL interface levels.
Pullup Reference clock inputs. LVCMOS / LVTTL interface levels.
Pullup Clock enable. LVCMOS / LVTTL interface levels.
Pullup Output enable. LVCMOS / LVTTL interface levels.
Core supply pin.
Description
10, 14, 18, 22, 27, 31
V
DDO
Power
Output supply pins.
11, 13, 15, 19, 21, 23, Q8, Q7, Q6, Q5, Q4,
Q0 thru Q8 clock outputs.
Output
26, 28, 30
Q3, Q2, Q1, Q0
LVCMOS / LVTTL interface levels.
NOTE:
Pullup
refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
C
PD
R
PULLUP
R
OUT
Parameter
Input Capacitance
Power Dissipation Capacitance
(per output)
Input Pullup Resistor
Output Impedance
Test Conditions
Minimum
Typical
4
12
51
7
Maximum
Units
pF
pF
KΩ
Ω
T
ABLE
3. O
UTPUT
E
NABLE AND
C
LOCK
E
NABLE
F
UNCTION
T
ABLE
Control Inputs
OE
0
1
1
CLK_EN
X
0
1
Output
Q0:Q8
Hi-Z
LOW
Follows CLK input
©2016 Integrated Device Technology, Inc
2
Revision A March 18, 2016
83947I-147 Data Sheet
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
DD
+ 0.5 V
-0.5V to V
DDO
+ 0.5V
47.9°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions
beyond those listed in the
DC Characteristics
or
AC Charac-
teristics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V±0.3V
OR
2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Core Supply Voltage
Output Supply Voltage
Input Supply Current
Output Supply Current
Test Conditions
Minimum
3.0
2.375
3.0
2.375
Typical
3.3
2.5
3.3
2.5
Maximum
3.6
2.625
3.6
2.625
50
9
Units
V
V
V
V
mA
mA
T
ABLE
4B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V±0.3V, T
A
= -40°C
TO
85°C
Symbol
V
IH
V
IL
I
IN
V
OH
V
OL
Parameter
Input High Voltage
Input Low Voltage
Input Current
CLK0, CLK1, OE,
CLK_SEL, CLK_EN
I
OH
= -20mA
I
OL
= 20mA
-100
2.5
0.4
Test Conditions
Minimum
2
Typical
Maximum
3.6
0.8
Units
V
V
µA
V
V
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
NOTE 1: Outputs terminated with 50Ω to V
DDO
/2. See Parameter Measurement Information Section,
3.3V Output Load Test
Circuit Diagram.
T
ABLE
4B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
V
IH
V
IL
I
IH
I
IL
V
OH
V
OL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
CLK0, CLK1
CLK_SEL, CLK_EN, OE
CLK0, CLK1, OE, CLK_
SEL, CLK_EN
CLK0, CLK1, OE, CLK_
SEL, CLK_EN
V
DD
= V
IN
= 2.625V
V
DD
= 32.625V,
V
IN
= 0V
-150
1.8
0.5
Test Conditions
Minimum
2
-0.3
-0.3
Typical
Maximum
V
DD
+ 0.3
1.3
0.8
5
Units
V
V
V
µA
µA
V
V
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
NOTE 1: Outputs terminated with 50Ω to V
DDO
/2. See Parameter Measurement Information Section,
2.5V Output Load Test
Circuit Diagram.
©2016 Integrated Device Technology, Inc
3
Revision A March 18, 2016
83947I-147 Data Sheet
T
ABLE
5A. AC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V±0.3V, T
A
= -40°C
TO
85°C
Symbol
f
MAX
t
PD
tsk(o)
tsk(pp)
tjit(Ø)
t
R
/ t
F
t
PW
odc
t
EN
t
DIS
t
S
Parameter
Output Frequency
Propagation Delay, NOTE 1
Output Skew; NOTE 2, 5
Part-to-Part Skew; NOTE 3, 5
Buffer Additive Phase Jitter,
RMS; refer to Additive Phase
Jitter Section
Output Rise/Fall Time
Output Pulse Width
Output Duty Cycle
Output Enable Time; NOTE 4
Output Disable Time; NOTE 4
Clock Enable Setup Time
0
Test Conditions
f
≤
250MHZ
Measured on
rising edge @V
DDO
/2
Measured on
rising edge @V
DDO
/2
(12KHz to 20MHz)
0.8V to 2.0V
f > 133MHz
f
≤
133MHz
0.2
t
Period
/2 - 1
40
0.2
1
t
Period
/2 + 1
60
10
10
Minimum
2
Typical
Maximum
250
4.2
115
500
Units
MHz
ns
ps
ps
ps
ns
ns
%
ns
ns
ns
t
S
Clock Enable Hold Time
1
ns
All parameters measured at frequencies less than or equal to 250MHz unless noted otherwise.
NOTE 1: Measured from V
DD
/2 of the input to V
DDO
/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V
DDO
/2.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with
equal load conditions. Using the same type of inputs on each device, the outputs are measured at V
DDO
/2.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
T
ABLE
5B. AC C
HARACTERISTICS
,
V
DD
= V
DDO
= 2.5V ± 5%, T
A
= -40°C
TO
85°C
Symbol
f
MAX
t
PD
tsk(o)
tsk(pp)
tjit(Ø)
t
R
/ t
F
t
PW
t
EN
t
DIS
t
S
Parameter
Output Frequency
Propagation Delay, NOTE 1
Output Skew; NOTE 2, 5
Part-to-Part Skew; NOTE 3, 5
Buffer Additive Phase Jitter,
RMS; refer to Additive Phase
Jitter Section
Output Rise/Fall Time
Output Pulse Width
Output Enable Time; NOTE 4
Output Disable Time; NOTE 4
Clock Enable Setup Time
0
Test Conditions
f
≤
250MHZ
Measured on
rising edge @V
DDO
/2
Measured on
rising edge @V
DDO
/2
(12KHz to 20MHz)
20% - 80%
300
t
Period
/2 - 1.2
0.1
800
t
Period
/2 + 1.2
10
10
Minimum
2.4
Typical
Maximum
250
4.5
130
600
Units
MHz
ns
ps
ps
ps
ps
ns
ns
ns
ns
t
S
Clock Enable Hold Time
1
ns
All parameters measured at frequencies less than or equal to 250MHz unless noted otherwise.
NOTE 1: Measured from V
DD
/2 of the input to V
DDO
/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V
DDO
/2.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with
equal load conditions. Using the same type of inputs on each device, the outputs are measured at V
DDO
/2.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
©2016 Integrated Device Technology, Inc
4
Revision A March 18, 2016
83947I-147 Data Sheet
A
DDITIVE
P
HASE
J
ITTER
The spectral purity in a band at a specific offset from the fun-
damental compared to the power of the fundamental is called
the
dBc Phase Noise.
This value is normally expressed using
a Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the fun-
damental frequency to the power value of the fundamental. This
ratio is expressed in decibels (dBm) or a ratio of the power in the
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
1k
1Hz band to the power in the fundamental. When the required
offset is specified, the phase noise is called a
dBc
value, which
simply means dBm at a specified offset from the fundamental.
By investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the
entire time record of the signal. It is mathematically possible to
calculate an expected bit error rate given a phase noise plot.
Additive Phase Jitter, RMS
@
156.25MHz (12KHz to 20MHz)
= 0.02ps typical @ 3.3V
SSB P
HASE
N
OISE
dBc/H
Z
10k
100k
1M
10M
100M
O
FFSET
F
ROM
C
ARRIER
F
REQUENCY
(H
Z
)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
1k
Additive Phase Jitter, RMS
@
156.25MHz (12KHz to 20MHz)
= 0.01ps typical @ 2.5V
SSB P
HASE
N
OISE
dBc/H
Z
10k
100k
1M
10M
100M
O
FFSET
F
ROM
C
ARRIER
F
REQUENCY
(H
Z
)
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher
than the noise floor of the device. This is illustrated above. The
device meets the noise floor of what is shown, but can actually
be lower. The phase noise is dependant on the input source and
measurement equipment.
©2016 Integrated Device Technology, Inc
5
Revision A March 18, 2016
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