Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any
other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
8 SOT23
PACKAGE CODE
Outline Number
Land Pattern Number
Thermal Resistance, Single-Layer Board
Junction-to-Ambient (q
JA
)
Junction-to-Case (q
JC
)
Thermal Resistance, Four-Layer Board
Junction-to-Ambient (q
JA
)
Junction-to-Case (q
JC
)
K8+5
21-0078
90-0176
N/A
800
196
70
For the latest package outline information and land patterns (footprints), go to
www.maximintegrated.com/packages.
Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board.
For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Electrical Characteristics
PARAMETER
Supply Voltage
(V
CC
= +1.2V to +5.5V, T
A
= T
MIN
to T
MAX
, unless otherwise specified. Typical values are at V
CC
= +5V and T
A
= +25°C.) (Note 1)
SYMBOL
V
CC
CONDITIONS
T
A
= 0°C to +125°C
T
A
= -40°C to 0°C
V
CC
≤ 5.5V
Supply Current
I
CC
V
CC
≤ 3.3V
V
CC
≤ 2.0V
V
CC
Reset Threshold
Hysteresis
V
CC
Reset Threshold
(MAX6752AKA32 Only)
Hysteresis (MAX6752AKA32 Only)
V
CC
to Reset Delay
Reset Timeout Period
SRT Ramp Current
SRT Ramp Threshold
t
RP
I
RAMP
V
RAMP
V
TH
V
HYST
TA = -40°C to +125°C
V
HYST
V
CC
falling from V
TH
+ 100mV to V
TH
-100mV at 1mV/µs
C
SRT
= 1500pF
C
SRT
= 100pF
V
SRT
= 0 to 1.23V; V
CC
= 1.6V to 5V
V
CC
= 1.6V to 5V (V
RAMP
rising)
200
1.173
5.692
3.136
0.65
0.80
20
7.590
0.506
250
1.235
300
1.297
9.487
See V
TH
selection table
T
A
= -40°C to +125°C
V
TH
-
2%
0.8
3.224
0.90
MIN
1.0
1.2
5
4.2
3.7
TYP
MAX
5.5
5.5
10
9
8
V
TH
+
2%
V
%
V
%
µs
ms
nA
V
µA
UNITS
V
www.maximintegrated.com
Maxim Integrated │ 2
MAX6746–MAX6753
μP Reset Circuits with Capacitor-Adjustable
Reset/Watchdog Timeout Delay
Electrical Characteristics (continued)
PARAMETER
Normal Watchdog Timeout Period
(MAX6746–MAX6751)
Extended Watchdog Timeout
(MAX6746–MAX6751)
Slow Watchdog Period
(MAX6752/MAX6753)
Fast Watchdog Timeout Period,
SET Ratio = 8,
(MAX6752/MAX6753)
Fast Watchdog Timeout Period,
SET Ratio = 16,
(MAX6752/MAX6753)
Fast Watchdog Timeout Period,
SET Ratio = 64,
(MAX6752/MAX6753)
Fast Watchdog Minimum Period
(MAX6752/MAX6753)
SWT Ramp Current
SWT Ramp Threshold
RESET
Output-Voltage Low
Open-Drain, Push-Pull
(Asserted)
RESET
Output-Voltage High,
Push-Pull (Not Asserted)
RESET
Output Leakage Current,
Open Drain
I
RAMP
V
RAMP
V
OL
SYMBOL
t
WD
t
WD
t
WD2
t
WD1
(V
CC
= +1.2V to +5.5V, T
A
= T
MIN
to T
MAX
, unless otherwise specified. Typical values are at V
CC
= +5V and T
A
= +25°C.) (Note 1)
CONDITIONS
C
SWT
= 1500pF
C
SWT
= 100pF
C
SWT
= 1500pF
C
SWT
= 100pF
C
SWT
= 1500pF
C
SWT
= 100pF
C
SWT
= 1500pF
C
SWT
= 100pF
C
SWT
= 1500pF
C
SWT
= 100pF
C
SWT
= 1500pF
C
SWT
= 100pF
2000
V
SWT
= 0 to 1.23V, V
CC
= 1.6V to 5V
V
CC
= 1.6V to 5V (V
RAMP
rising)
V
CC
≥ 1.0V, I
SINK
= 50µA
V
CC
≥ 2.7V, I
SINK
= 1.2mA
V
CC
≥
4.5V, I
SINK
= 3.2mA
V
CC
≥ 1.8V, I
SOURCE
= 200µA
V
OH
V
CC
≥ 2.25V, I
SOURCE
= 500µA
V
CC
≥ 4.5V, I
SOURCE
= 800µA
I
LKG
V
CC
> V
TH
, reset not asserted,
V
RESET
= 5.5V
0.8 x V
CC
0.8 x V
CC
0.8 x V
CC
1.0
µA
V
200
1.173
250
1.235
300
1.297
0.3
0.3
0.4
V
11.38
45.53
91.08
728.6
728.6
MIN
5.692
TYP
7.590
0.506
971.5
64.77
971.5
64.77
121.43
8.09
60.71
4.05
15.18
1.01
18.98
75.89
151.80
1214.4
1214.4
MAX
9.487
UNITS
ms
ms
ms
ms
t
WD1
ms
t
WD1
ms
ns
nA
V
DIGITAL INPUTS (MR, SET0, SET1, WDI, WDS)
V
IL
Input Logic Levels
V
IH
V
IL
V
IH
MR
Minimum Pulse Width
MR
Glitch Rejection
MR-to-RESET
Delay
MR
Pullup Resistance
WDI Minimum Pulse Width
Pullup to V
CC
12
300
V
CC
≥
4.0V
V
CC
< 4.0V
0.7 x V
CC
1
100
200
20
28
µs
ns
ns
kΩ
ns
0.8
2.4
0.3 x V
CC
V
www.maximintegrated.com
Maxim Integrated │
3
MAX6746–MAX6753
μP Reset Circuits with Capacitor-Adjustable
Reset/Watchdog Timeout Delay
Electrical Characteristics (continued)
PARAMETER
RESET IN
RESET IN Threshold
RESET IN Leakage Current
RESET IN to
RESET
Delay
V
RESET IN
I
RESET IN
SYMBOL
(V
CC
= +1.2V to +5.5V, T
A
= T
MIN
to T
MAX
, unless otherwise specified. Typical values are at V
CC
= +5V and T
A
= +25°C.) (Note 1)
CONDITIONS
T
A
= -40°C to +125°C
RESET IN falling at 1mV/µs
MIN
1.216
-50
TYP
1.235
±1
20
MAX
1.254
+50
UNITS
V
nA
µs
Note 1:
Production testing done at T
A
= +25°C. Over temperature limits are guaranteed by design.
卡巴斯基的安全研究人员称其发现了如何攻击Intel微处理器的远程攻击代码，据传，这一代码可以通过TCP/IP包和JavaScript代码到达用户系统。 目前受影响的系统包括Windows XP，Vista，Windows Server 2003，Windows Server 2008，Linux甚至是BSD和Mac。但所幸大多数错误可以由Intel和BIOS厂商联合进行修复。 卡...[详细]
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