ICS87951I
L
OW
S
KEW
, 1-
TO
-9
D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL Z
ERO
D
ELAY
B
UFFER
G
ENERAL
D
ESCRIPTION
The ICS87951I is a low voltage, low skew 1-to-9
Differential-to-LVCMOS/LVTTL Cock Generator. The
CS87951I has two selectable clock inputs. The single ended
clock input accepts LVCMOS or LVTTL input
levels. The CLK1, nCLK1 pair can accept most standard
differential input levels. With output frequencies up to 180MHz,
the ICS87951I is targeted for high performance clock appli-
cations. Along with a fully integrated PLL, the ICS87951I con-
tains frequency configurable outputs and an external
feedback input for regenerating clocks with “zero delay”.
F
EATURES
•
Fully integrated PLL
•
Nine single ended 3.3V LVCMOS/LVTTL outputs
•
Selectable single ended CLK0 or differential
CLK1, nCLK1 inputs
•
The single ended CLK0 input can accept the following
input levels: LVCMOS or LVTTL input levels
•
CLK1, nCLK1 supports the following input types:
LVDS, LVPECL, LVHSTL, SSTL, HCSL
•
Output frequency range: 25MHz to 180MHz
•
VCO range: 200MHz to 480MHz
•
External feedback for ”zero delay” clock regeneration
•
Cycle-to-cycle jitter: ±100ps (typical)
•
Output skew: 375ps (maximum)
•
PLL reference zero delay: 350ps window (maximum)
•
3.3V operating supply
•
-40°C to 85°C ambient operating temperature
•
Available in both standard and lead-free RoHS-compliant
packages
P
IN
A
SSIGNMENT
CLK_SEL
PLL_SEL
CLK0
GND
GND
V
DDO
QB
QA
32 31 30 29 28 27 26 25
V
DDA
EXT_FB
DIV_SELA
DIV_SELB
DIV_SELC
DIV_SELD
GND
CLK1
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
nCLK1
MR/nOE
V
DDO
QD4
GND
QD3
V
DDO
QD2
24
23
22
QC0
V
DDO
QC1
GND
QD0
V
DDO
QD1
GND
ICS87951I
21
20
19
18
17
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y package
Top View
87951AYI
www.idt.com
1
REV. C JULY 17, 2010
ICS87951I
L
OW
S
KEW
, 1-
TO
-9
D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL Z
ERO
D
ELAY
B
UFFER
B
LOCK
D
IAGRAM
DIV_SELA
Internal Pulldown
PLL_SEL
Internal Pulldown
CLK0
Internal Pulldown
CLK_SEL
Internal Pulldown
nCLK1
CLK1
Internal
Pulldown/
Pullup
1
0
PHASE
DETECTOR
VCO
200-480MHz
0
1
÷2
÷4
÷8
0
QA
1
0
LPF
1
EXT_FB
Internal Pullup
DIV_SELB
Internal Pulldown
QB
0
1
QC0
QC1
DIV_SELC
Internal Pulldown
MR/nOE
Internal Pulldown
POWER-ON RESET
0
1
DIV_SELD
Internal Pulldown
QD0
QD1
QD2
QD3
QD4
87951AYI
www.idt.com
2
REV. C JULY 17, 2010
ICS87951I
L
OW
S
KEW
, 1-
TO
-9
D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL Z
ERO
D
ELAY
B
UFFER
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2
3
4
5
6
7, 13, 17,
21, 25, 29
8
9
10
11, 15,
19, 23, 27
12, 14,
16, 18, 20
22, 24
26
28
30
31
32
Name
V
DDA
EXT_FB
DIV_SELA
DIV_SELB
DIV_SELC
DIV_SELD
GND
CLK1
nCLK1
MR/nOE
Type
Power
Input
Input
Input
Input
Input
Power
Input
Input
Input
Pullup
Pullup
Pulldown
Pulldown
Pulldown
Pulldown
Description
Analog supply pin.
Feedback input to phase detector for regenerating clocks with
"zero delay". LVCMOS / LVTTL interface levels.
Selects divide value for Bank A output as described in Table 3D.
LVCMOS / LVTTL interface levels.
Selects divide value for Bank B output as described in Table 3D.
LVCMOS / LVTTL interface levels.
Selects divide value for Bank C outputs as described in Table 3D.
LVCMOS / LVTTL interface levels.
Selects divide value for Bank D outputs as described in Table 3D.
LVCMOS / LVTTL interface levels.
Power supply ground.
Non-inver ting differential clock input.
Pulldown Inver ting differential clock input.
Active HIGH Master Reset. Active LOW output enable. When logic
HIGH, the internal dividers are reset and the outputs are tri-stated
Pulldown
(HiZ). When logic LOW, the internal dividers and the outputs are
enabled. LVCMOS / LVTTL interface levels.
Output supply pins.
Bank D clock outputs. 7
Ω
typical output impedance.
LVCMOS / LVTTL interface levels.
Bank C clock outputs. 7
Ω
typical output impedance.
LVCMOS / LVTTL interface levels.
Bank B clock output. 7
Ω
typical output impedance.
LVCMOS / LVTTL interface levels.
Bank A clock output. 7
Ω
typical output impedance.
LVCMOS / LVTTL interface levels.
Pulldown LVCMOS / LVTTL phase detector reference clock input.
Selects between the PLL and the reference clock as the input to the
Pulldown dividers. When HIGH, selects PLL. When LOW, selects the reference
clock. LVCMOS / LVTTL interface levels.
Clock select input. When HIGH, selects CLK0. When LOW,
Pulldown
selects CLK1, nCLK1. LVCMOS / LVTTL interface levels.
V
DDO
QD4, QD3,
QD2, QD1, QD0
QC1, QC0
QB
QA
CLK0
PLL_SEL
CLK_SEL
Power
Output
Output
Output
Output
Input
Input
Input
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
C
PD
R
PULLUP
R
PULLDOWN
R
OUT
Parameter
Input Capacitance
Power Dissipation Capacitance (per output)
Input Pullup Resistor
Input Pulldown Resistor
Output Impedance
5
V
DDA
, V
DDO
= 3.47V
Test Conditions
Minimum Typical
4
25
51
51
7
12
Maximum
Units
pF
pF
KΩ
KΩ
Ω
87951AYI
www.idt.com
3
REV. C JULY 17, 2010
ICS87951I
L
OW
S
KEW
, 1-
TO
-9
D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL Z
ERO
D
ELAY
B
UFFER
T
ABLE
3A. O
UTPUT
C
ONTROL
P
IN
F
UNCTION
T
ABLE
Inputs
MR/nOE
1
0
QA
HiZ
Enabled
QB
HiZ
Enabled
Outputs
QC0, QC1
HiZ
Enabled
QD0:QD4
HiZ
Enabled
T
ABLE
3B. O
PERATING
M
ODE
F
UNCTION
T
ABLE
Inputs
PLL_SEL
0
1
Operating Mode
Bypass
PLL
T
ABLE
3C. PLL I
NPUT
F
UNCTION
T
ABLE
Inputs
CLK_SEL
0
1
PLL Input
CLK1, nCLK1
CLK0
T
ABLE
3D. P
ROGRAMMABLE
O
UTPUT
F
REQUENCY
F
UNCTION
T
ABLE
Inputs
DIV_SELA
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
DIV_SELB
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
DIV_SELC
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
DIV_SELD
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
QA
VCO/2
VCO/2
VCO/2
VCO/2
VCO/2
VCO/2
VCO/2
VCO/2
VCO/4
VCO/4
VCO/4
VCO/4
VCO/4
VCO/4
VCO/4
VCO/4
QB
VCO/4
VCO/4
VCO/4
VCO/4
VCO/8
VCO/8
VCO/8
VCO/8
VCO/4
VCO/4
VCO/4
VCO/4
VCO/8
VCO/8
VCO/8
VCO/8
Outputs
QCx
VCO/4
VCO/4
VCO/8
VCO/8
VCO/4
VCO/4
VCO/8
VCO/8
VCO/4
VCO/4
VCO/8
VCO/8
VCO/4
VCO/4
VCO/8
VCO/8
QDx
VCO/4
VCO/8
VCO/4
VCO/8
VCO/4
VCO/8
VCO/4
VCO/8
VCO/4
VCO/8
VCO/4
VCO/8
VCO/4
VCO/8
VCO/4
VCO/8
87951AYI
www.idt.com
4
REV. C JULY 17, 2010
ICS87951I
L
OW
S
KEW
, 1-
TO
-9
D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL Z
ERO
D
ELAY
B
UFFER
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
DDA
+ 0.5 V
-0.5V to V
DDO
+ 0.5V
42.1°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DDA
= V
DDO
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
DDA
V
DDO
I
DDO
I
DDA
Parameter
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
All V
DD
pins
Test Conditions
Minimum
3.135
3.135
Typical
3.3
3.3
Maximum
3.465
3.465
115
20
Units
V
V
mA
mA
T
ABLE
4B. DC C
HARACTERISTICS
,
V
DDA
= V
DDO
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol Parameter
CLK0
DIV_SELA:DIV_SELD,
PLL_SEL, CLK_SEL,
EXT_FB, MR/nOE
CLK0
DIV_SELA:DIV_SELD,
PLL_SEL, CLK_SEL,
EXT_FB, MR/nOE
Test Conditions
Minimum
2
2
-0.3
-0.3
300
GND + 0.5
I
OH
= -40mA
I
OL
= 40mA
2.4
0.5
±120
Typical
Maximum
V
DD
+ 0.3
V
DD
+ 0.3
1.3
0.8
1000
V
DD
- 0.85
Units
V
V
V
V
mV
V
V
V
µA
V
IH
Input High Voltage
V
IL
Input Low Voltage
V
PP
V
CMR
V
OH
V
OL
Peak-to-Peak
CLK1, nCLK1
Input Voltage
Common Mode Input Voltage; NOTE 1, 2
Output High Voltage
Output Low Voltage
I
IN
Input Current
NOTE 1: Common mode voltage is defined as V
IH
.
NOTE 2: For single ended applications, the maximum input voltage for CLK1 and nCLK1 is V
DDA
+ 0.3V.
87951AYI
www.idt.com
5
REV. C JULY 17, 2010
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