IDT74FCT3244/A
3.3V CMOS OCTAL BUFFER/LINE DRIVER
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS OCTAL
BUFFER/LINE DRIVER
IDT74FCT3244/A
• 0.5 MICRON CMOS Technology
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• V
CC
= 3.3V ±0.3V, Normal Range
• V
CC
= 2.7V to 3.6V, Extended Range
μ
• CMOS power levels (0.4μW typ. static)
• Rail-to-Rail output swing for increased noise margin
• Available in QSOP, SOIC, SSOP, and TSSOP packages
FEATURES:
DESCRIPTION:
The FCT3244/A octal buffer/line drivers are built using advanced dual
metal CMOS technology. These high-speed, low-power buffers are
designed to be used as memory data and address drivers, clock drivers,
and bus-oriented transmitter/receivers. The three-state controls are
designed to operate these devices in a dual-nibble or single-byte mode. All
inputs are designed with hysteresis for improved noise margin.
FUNCTIONAL BLOCK DIAGRAM
1
OE
1
A
1
1
A
2
1
A
3
1
A
4
1
2
4
6
8
18
16
14
12
1
Y
1
1
Y
2
1
Y
3
1
Y
4
2
OE
2
A
1
2
A
2
2
A
3
2
A
4
19
11
13
15
17
9
7
5
3
2
Y
1
2
Y
2
2
Y
3
2
Y
4
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
MAY 2018
DSC-2779/16
©2018
Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM(2)
V
TERM(3)
V
TERM(4)
T
STG
I
OUT
Description
Terminal Voltage with Respect to GND
Terminal Voltage with Respect to GND
Terminal Voltage with Respect to GND
Storage Temperature
DC Output Current
Max
–0.5 to +4.6
–0.5 to +7
–0.5 to V
CC
+0.5
–65 to +150
–60 to +60
Unit
V
V
V
°C
mA
1
OE
1
A
1
2
Y
4
1
A
2
2
Y
3
1
A
3
2
Y
2
1
A
4
2
Y
1
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Vcc
2
OE
1
Y
1
2
A
4
1
Y
2
2
A
3
1
Y
3
2
A
2
1
Y
4
2
A
1
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. V
CC
terminals.
3. Input terminals.
4. Outputs and I/O terminals.
GND
TOP VIEW
CAPACITANCE
(T
A
= +25°C, F = 1.0MHz)
Order Code
QG
SOG
PGG
PYG
Symbol
C
IN
C
OUT
Parameter
(1)
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Typ.
3.5
4
Max.
6
8
Unit
pF
pF
Package Type
QSOP
SOIC
TSSOP
SSOP
Package Code
PCG20
PSG20
PGG20
PYG20
NOTE:
1. This parameter is measured at characterization but not tested.
PIN DESCRIPTION
Pin Names
xOE
xAx
xYx
Data Inputs
3-State Outputs
Description
3–State Output Enable Inputs (Active LOW)
FUNCTION TABLE
(1)
Inputs
xOE
L
L
H
NOTE:
1. H = HIGH Voltage Level
X = Don’t Care
L = LOW Voltage Level
Z = High Impedance
Outputs
xAx
L
H
X
xYx
L
H
Z
2
IDT74FCT3244/A
3.3V CMOS OCTAL BUFFER/LINE DRIVER
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: T
A
= -40°C to +85°C, V
CC
= 2.7V to 3.6V
Symbol
V
IH
V
IL
I
IH
I
IL
I
OZH
I
OZL
V
IK
I
ODH
I
ODL
V
OH
Parameter
Input HIGH Level (Input pins)
Input HIGH Level (I/O pins)
Input LOW Level
(Input and I/O pins)
Input HIGH Current (Input pins)
Input HIGH Current (I/O pins)
Input LOW Current (Input pins)
Input LOW Current (I/O pins)
High Impedance Output Current
(3-State Output pins)
Clamp Diode Voltage
Output HIGH Current
Output LOW Current
Output HIGH Voltage
V
CC
= Min., I
IN
= –18mA
V
CC
= 3.3V, V
IN
= V
IH
or V
IL
, V
O
= 1.5V
(3)
V
CC
= 3.3V, V
IN
= V
IH
or V
IL
, V
O
= 1.5V
(3)
V
CC
= Min.
V
IN
= V
IH
or V
IL
V
CC
= 3V
V
IN
= V
IH
or V
IL
V
OL
Output LOW Voltage
V
CC
= Min.
V
IN
= V
IH
or V
IL
V
CC
= 3V
V
IN
= V
IH
or V
IL
I
OS
V
H
I
CCL
I
CCH
I
CCZ
Short Circuit Current
(4)
Input Hysteresis
Quiescent Power Supply Current
V
CC
= Max., V
O
= GND
(3)
—
V
CC
= Max., V
IN
= GND or V
CC
–60
—
—
–135
150
0.1
–240
—
10
mA
mV
µA
I
OL
= 0.1mA
I
OL
= 16mA
I
OL
= 24mA
I
OL
= 24mA
—
—
—
—
0.2
0.3
0.3
0.2
0.4
0.55
0.5
V
I
OH
= –0.1mA
I
OH
= –3mA
I
OH
= –8mA
V
CC
= Max.
V
CC
= Max.
V
I
= 5.5V
V
I
= V
CC
V
I
= GND
V
I
= GND
V
O
= V
CC
V
O
= GND
—
—
—
—
—
—
—
–36
50
V
CC
–0.2
2.4
2.4
(5)
—
—
—
—
—
—
–0.7
–60
90
—
3
3
±1
±1
±1
±1
±1
±1
–1.2
–110
200
—
—
—
V
mA
mA
V
µA
µA
Guaranteed Logic LOW Level
Test Conditions
(1)
Guaranteed Logic HIGH Level
Min.
2
2
–0.5
Typ.
(2)
—
—
—
Max.
5.5
Vcc+0.5
0.8
V
Unit
V
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 3.3V, +25°C ambient and maximum loading.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. This parameter is guaranteed but not tested.
5. V
OH
= V
CC
- 0.6V at rated current.
3
POWER SUPPLY CHARACTERISTICS
Symbol
I
CC
I
CCD
Parameter
Quiescent Power Supply Current
Dynamic Power Supply
Current
(4)
V
CC
= Max.
V
CC
= Max.
Outputs Open
xOE = GND
One Input Toggling
50% Duty Cycle
I
C
Total Power Supply Current
(6)
V
CC
= Max.
Outputs Open
f
I
= 10MHz
50% Duty Cycle
xOE = GND
One Bit Toggling
V
CC
= Max.
Outputs Open
f
I
= 2.5MHz
50% Duty Cycle
xOE = GND
Eight Bits Toggling
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 3.3V, +25°C ambient.
3. Per TTL driven input. All other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of
ΔI
CC
formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
ΔI
CC
D
H
N
T
+ I
CCD
(f
CP
N
CP
/2 + fiNi)
I
CC
= Quiescent Current (I
CC
, I
CCH
, and I
CCZ
)
ΔI
CC
= Power Supply Current for a TTL High Input
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current caused by an Input Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for register devices (zero for non-register devices)
N
CP
= Number of clock inputs at f
CP
fi = Input Frequency
Ni = Number of Inputs at fi
Test Conditions
(1)
V
IN
= V
CC
- 0.6V
V
IN
= V
CC
V
IN
= GND
Min.
—
—
Typ.
(2)
2
60
Max.
30
85
Unit
μA
μA/
MHz
V
IN
= V
CC
V
IN
= GND
V
IN
= V
CC
- 0.6V
V
IN
= GND
V
IN
= V
CC
V
IN
= GND
V
IN
= V
CC
- 0.6V
V
IN
= GND
—
0.6
0.9
mA
—
0.6
0.9
—
1.2
1.7
(5)
—
1.2
1.8
(5)
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
(1)
74FCT3244
Symbol
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Parameter
Propagation Delay
xAx to xYx
Output Enable Time
Output Disable Time
Condition
C
L
= 50pF
R
L
= 500Ω
(2)
Min.
1.5
1.5
1.5
(3)
Max.
6.5
8
7
74FCT3244A
Min.
Max.
1.5
4.8
(3)
Unit
ns
ns
ns
1.5
1.5
6.2
5.6
NOTES:
1. Propagation Delays and Enable/Disable times are with V
CC
= 3.3V ±0.3V, Normal Range. For V
CC
= 2.7V to 3.6V, Extended Range, all Propagation Delays and Enable/
Disable times should be degraded by 20%.
2. See test circuit and waveforms.
3. Minimum limits are guaranteed but not tested on Propagation Delays.
4
IDT74FCT3244/A
3.3V CMOS OCTAL BUFFER/LINE DRIVER
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
V
CC
500Ω
V
IN
Pulse
Generator
R
T
D.U.T.
50pF
C
L
500Ω
V
OUT
6v
Open
GND
SWITCH POSITION
Test
Open Drain
Disable Low
Enable Low
Disable High
Enable High
All Other Tests
Switch
6V
GND
Open
Test Circuits for All Outputs
DEFINITIONS:
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
= Termination resistance: should be equal to Z
OUT
of the Pulse Generator.
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
PRESET
CLEAR
CLOCK ENABLE
ETC.
t
SU
t
H
t
REM
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
LOW-HIGH-LOW
PULSE
t
W
HIGH-LOW-HIGH
PULSE
1.5V
1.5V
t
SU
t
H
Pulse Width
Set-Up, Hold, and Release Times
ENABLE
CONTROL
INPUT
SAME PHASE
INPUT TRANSITION
t
PLH
OUTPUT
t
PLH
OPPOSITE PHASE
INPUT TRANSITION
t
PHL
t
PHL
3V
1.5V
0V
V
OH
1.5V
V
OL
3V
1.5V
0V
t
PZL
OUTPUT
NORMALLY
LOW
OUTPUT
NORMALLY
HIGH
SWITCH
6V
t
PZH
SWITCH
GND
1.5V
0V
3V
1.5V
DISABLE
3V
1.5V
0V
3V
0.3V
t
PHZ
0.3V
V
OH
0V
V
OL
t
PLZ
Propagation Delay
Enable and Disable Times
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
2. Pulse Generator for All Pulses: Rate
≤
1.0MHz; Z
O
≤
50Ω; t
F
≤
2.5ns; t
R
≤
2.5ns.
3. If Vcc is below 3V, input voltage swings should be adjusted not to exceed Vcc.
5
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