Si5356A
I
2
C P
ROGRAMMABLE
, A
NY
- F
R E Q U E N C Y
1 – 2 0 0 M H
Z
,
Q
UAD
F
R E Q U E N C Y
8-O
UTPUT
C
LOCK
G
ENERATOR
Features
Generates any frequency from 1 to
200 MHz on each of the 4 output banks
Programmable frequency configuration
Guaranteed 0 ppm frequency synthesis
error for any combination of frequencies
25 or 27 MHz xtal or 5–200 MHz input clk
Eight CMOS clock outputs
Easy to use programming software
Configurable “triple A” spread spectrum:
any
clock,
any
frequency, and with
any
spread amount
Programmable output phase adjustment
with <20 ps error
Interrupt pin indicates LOS or LOL
OEB pin disables all outputs or per
bank OEB control via I
2
C
Low jitter: 50 ps pk-pk (typ), 75 ps
pk-pk period jitter (max)
Excellent PSRR performance
eliminates need for external power
supply filtering
Low power: 45 mA (core)
Core VDD: 1.8, 2.5, or 3.3 V
Separate VDDO for each bank of
outputs: 1.8, 2.5, or 3.3 V
Small size: 4x4 mm 24-QFN
Industrial temperature range:
–40 to +85 °C
Ordering Information:
See page 23.
Pin Assignments
Applications
Printers
Audio/video
DSLAM
Storage area networks
Switches/routers
Servers
XAXA
1 1
XBXB
2 2
I2C_LSB
3 3
P1
CLKIN
4 4
CLKIN
SSC_DIS
5 5
P4
OEB
P5
6 6
Top View
Top View
CLK0
CLK0
GND
GND
CLK1
CLK1
VDD
VDD
VDDOA
VDDOA
20
20
11
11
24 24 2323 22
22
21
21
19
19
18
CLK2
18
CLK2
17
CLK3
17
CLK3
16
VDDOB
16
VDDOB
Description
The Si5356 is a highly flexible, I
2
C programmable clock generator capable of
synthesizing four completely non-integer related frequencies up to 200 MHz. The
device has four banks of outputs with each bank supporting two CMOS outputs at
the same frequency. Using Silicon Laboratories' patented MultiSynth fractional
divider technology, all outputs are guaranteed to have 0 ppm frequency synthesis
error regardless of configuration, enabling the replacement of multiple clock ICs
and crystal oscillators with a single device. Each output bank is independently
configurable to support 1.8, 2.5, or 3.3 V. The device is programmable via an I
2
C/
SMBus-compatible serial interface and supports operation from a 1.8, 2.5, or
3.3 V core supply.
GND
GND
GND
GND
P3
SDA
15
VDDOC
15
VDDOC
14
CLK4
14
CLK4
13
CLK5
13
CLK5
12
12
7 7
8 8
99
10
10
LOS
INTR
Functional Block Diagram
Rev. 1.2 1/13
Copyright © 2013 by Silicon Laboratories
VDDOD
VDDOD
VDD
VDD
CLK7
CLK7
CLK6
CLK6
P2
SCL
Si5356A
Si5356A
T
ABLE
Section
OF
C
ONTENTS
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Typical Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3.2. Input Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.3. Breakthrough MultiSynth Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.4. Frequency Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.5. Configuring the Si5356 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.6. Output Phase Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.7. CMOS Output Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.8. Jitter Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.9. Status Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.10. I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.11. Spread Spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.12. Power Supply Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4. Si5356 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.1. Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7. Package Outline: 24-Lead QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
8. Recommended PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
9. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
9.1. Si5356A Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
9.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Rev. 1.2
3
Si5356A
1. Electrical Specifications
Table 1. Recommended Operating Conditions
(V
DD
= 1.8 V –5% to +10%, 2.5 or 3.3 V ±10%, T
A
= –40 to 85 °C)
Parameter
Ambient Temperature
Core Supply Voltage
Symbol
T
A
V
DD
Test Condition
Min
–40
2.97
2.25
1.71
Typ
—
3.3
2.5
1.8
—
Max
85
3.63
2.75
1.98
3.63
Unit
o
C
V
Output Buffer Supply Voltage
V
DDO
1.71
V
Note:
All minimum and maximum specifications are guaranteed and apply across the recommended operating
conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless
otherwise noted.
Table 2. DC Characteristics
(V
DD
= 1.8 V –5% to +10%, 2.5 or 3.3 V ±10%, T
A
= –40 to 85 °C)
Parameter
Core Supply Current
Output Buffer Supply Current
Symbol
I
DD
I
DDOx
Test Condition
100 MHz on all outputs,
25 MHz refclk
CMOS, 50 MHz
15 pF load
CMOS, 200 MHz
3.3 V VDD0
CMOS, 200 MHz
2.5 V
CMOS, 200 MHz
1.8 V
Min
—
—
—
—
—
0.8 x V
DD
0.85
–0.2
—
V
DDO
– 0.3
—
0
—
Typ
45
6
13
10
7
—
—
—
—
—
—
—
20
Max
60
9
18
14
10
3.63
1.3
0.2 x V
DD
0.3
—
0.3
0.4
—
Unit
mA
mA
mA
mA
mA
V
V
V
V
V
V
V
k
High Level Input Voltage
V
IH
CLKIN, I2C_LSB
SSC_DIS, OEB
Low Level Input Voltage
V
IL
CLKIN, I2C_LSB
SSC_DIS, OEB
Clock Output High Level Output
Voltage
Clock Output Low Level Out-
put Voltage
INTR Low Level Output Voltage
SSC_DIS, OEB Input
Resistance
V
OH
V
OL
V
OLINTR
R
IN
Pins: CLK0–7
I
OH
= –4 mA
Pins: CLK0–7
I
OL
= +4 mA
Pin: INTR
I
OL
= +3 mA
4
Rev. 1.2
Si5356A
Table 3. AC Characteristics
(V
DD
= 1.8 V –5% to +10%, 2.5 or 3.3 V ±10%, T
A
= –40 to 85 °C)
Parameter
Input Clock
Clock Input Frequency
Clock Input Rise/Fall Time
Clock Input Duty Cycle
Clock Input Capacitance
Output Clocks
Clock Output Frequency
Clock Output Frequency Synthesis
Resolution
Output Load Capacitance
Clock Output Rise/Fall Time
Clock Output Rise/Fall Time
Clock Output Duty Cycle
Powerup Time
Output Enable Time
Output-Output Skew
Period Jitter
Cycle-Cycle Jitter
Phase Jitter
PLL Loop Bandwidth
Interrupt Status Timing
CLKIN Loss of Signal Assert Time
CLKIN Loss of Signal Deassert
Time
Symbol
F
IN
T
R
/T
F
DC
C
IN
F
O
F
RES
C
L
T
R
/T
F
T
R
/T
F
DC
T
PU
T
OE
T
SKEW
J
PPKPK
J
CCPK
J
PH
F
BW
t
LOS
t
LOS_b
Test Condition
Min
5
Typ
—
—
—
—
2
Max
200
2.3
4
60
—
Unit
MHz
ns
ns
%
pF
20–80% V
DD
10–90% V
DD
Input tr/tf within specified
limits shown above
—
—
40
—
1
See "3.4. Frequency Con-
figuration" on page 11
0
—
20 to 80% V
DD
,
C
L
= 15 pF
20 to 80% V
DD
,
C
L
= 2 pF
Measured at V
DD
/2
POR to output clock valid
—
—
45
—
—
Outputs at same
frequency, f
OUT
> 5 MHz
10000 cycles*
10000 cycles*
12 kHz to 20 MHz
–150
—
—
—
—
—
0
—
—
0.45
50
—
—
—
50
40
2
1.6
200
1
15
2.0
0.85
55
2
10
+150
75
70
—
—
MHz
ppb
pF
ns
ns
%
ms
µs
ps
ps pk-pk
ps pk
ps rms
MHz
—
0.01
2.6
0.2
5
1
µs
µs
*Note:
Measured in accordance to JEDEC Standard 65.
Rev. 1.2
5
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