IS61LV6416
IS61LV6416L
64K x 16 HIGH-SPEED CMOS STATIC RAM
WITH 3.3V SUPPLY
FEATURES
• High-speed access time: 8, 10, 12 ns
• CMOS low power operation
— 61LV6416:
75 mW (typical) operating current
0.5 mW (typical) standby current
— 61LV6416L:
65 mW (typical) operating current
50 µW (typical) standby current
• TTL compatible interface levels
• Single 3.3V power supply
• Fully static operation: no clock or refresh
required
• Three state outputs
• Data control for upper and lower bytes
• Industrial temperature available
• Lead-free available
ISSI
NOVEMBER 2005
®
DESCRIPTION
The
ISSI
IS61LV6416/IS61LV6416L is a high-speed,
1,048,576-bit static RAM organized as 65,536 words by 16
bits. It is fabricated using
ISSI
's high-performance CMOS
technology. This highly reliable process coupled with
innovative circuit design techniques, yields access times
as fast as 8 ns with low power consumption.
When
CE
is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be
reduced down with CMOS input levels.
Easy memory expansion is provided by using Chip
Enable and Output Enable inputs,
CE
and
OE.
The active
LOW Write Enable (WE) controls both writing and reading
of the memory. A data byte allows Upper Byte (UB) and
Lower Byte (LB) access.
The IS61LV6416/IS61LV6416L is packaged in the JEDEC
standard 44-pin 400-mil SOJ, 44-pin TSOP-II, and 48-pin
mini BGA (6mm x 8mm).
FUNCTIONAL BLOCK DIAGRAM
A0-A15
DECODER
64K x 16
MEMORY ARRAY
V
DD
GND
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
I/O
DATA
CIRCUIT
COLUMN I/O
CE
OE
WE
UB
LB
CONTROL
CIRCUIT
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any
published information and before placing orders for products.
Integrated Silicon Solution, Inc.
Rev. I
11/22/05
1
IS61LV6416
IS61LV6416L
TRUTH TABLE
I/O PIN
Mode
Not Selected
Output Disabled
Read
WE
X
H
X
H
H
H
L
L
L
CE
H
L
L
L
L
L
L
L
L
OE
X
H
X
L
L
L
X
X
X
LB
X
X
H
L
H
L
L
H
L
UB
X
X
H
H
L
L
H
L
L
I/O0-I/O7
High-Z
High-Z
High-Z
D
OUT
High-Z
D
OUT
D
IN
High-Z
D
IN
I/O8-I/O15
High-Z
High-Z
High-Z
High-Z
D
OUT
D
OUT
High-Z
D
IN
D
IN
ISSI
V
DD
Current
I
SB
1
, I
SB
2
I
CC
I
CC
®
1
2
3
4
Write
I
CC
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
T
STG
P
T
I
OUT
Parameter
Terminal Voltage with Respect to GND
Storage Temperature
Power Dissipation
DC Output Current (LOW)
Value
–0.5 to V
DD
+0.5
–65 to +150
1.5
20
Unit
V
°C
W
mA
5
6
7
V
DD
(12 ns)
3.3V ± 10%
3.3V ± 10%
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
OPERATING RANGE
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
–40°C to +85°C
V
DD
(8,10 ns)
3.3V+10%,-5%
3.3V+10%,-5%
8
9
10
Max.
—
0.4
V
DD
+ 0.3
0.8
2
2
Unit
V
V
V
V
µA
µA
DC ELECTRICAL CHARACTERISTICS
(Over Operating Range)
Symbol
V
OH
V
OL
V
IH
V
IL
I
LI
I
LO
Parameter
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
(1)
Input Leakage
Output Leakage
GND
≤
V
IN
≤
V
DD
GND
≤
V
OUT
≤
V
DD
, Outputs Disabled
Test Conditions
V
DD
= Min., I
OH
= –4.0 mA
V
DD
= Min., I
OL
= 8.0 mA
Min.
2.4
—
2
–0.3
–2
–2
11
12
Notes:
1. V
IL
(min.) = –2.0V for pulse width less than 10 ns.
Integrated Silicon Solution, Inc.
Rev. I
11/22/05
3
IS61LV6416
IS61LV6416L
IS61LV6416
POWER SUPPLY CHARACTERISTICS
(1)
(Over Operating Range)
Symbol Parameter
I
CC
V
DD
Dynamic Operating
Supply Current
TTL Standby Current
(TTL Inputs)
CMOS Standby
Current (CMOS Inputs)
Test Conditions
V
DD
= Max.,
I
OUT
= 0 mA, f = f
MAX
V
DD
= Max.,
V
IN
= V
IH
or V
IL
CE
≥
V
IH
, f = 0
V
DD
= Max.,
CE
≥
V
DD
– 0.2V,
V
IN
≥
V
DD
– 0.2V, or
V
IN
≤
0.2V, f = 0
Com.
Ind.
typ.
(2)
Com.
Ind.
Com.
Ind.
typ.
(2)
-8 ns
Min. Max.
—
—
—
—
—
—
—
—
140
150
105
15
20
5
10
0.5
-10 ns
Min. Max.
—
—
—
—
—
—
—
—
120
130
95
15
20
5
10
0.5
ISSI
-12 ns
Min. Max.
—
—
—
—
—
—
—
—
100
110
75
15
20
5
10
0.5
®
Unit
mA
I
SB
1
mA
I
SB
2
mA
Note:
1. At f = f
MAX
, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at V
DD
=3.3V, T
A
=25
o
C. Not 100% Tested.
IS61LV6416L
POWER SUPPLY CHARACTERISTICS
(1)
(Over Operating Range)
Symbol Parameter
I
CC
V
DD
Dynamic Operating
Supply Current
TTL Standby Current
(TTL Inputs)
CMOS Standby
Current (CMOS Inputs)
Test Conditions
V
DD
= Max.,
I
OUT
= 0 mA, f = f
MAX
V
DD
= Max.,
V
IN
= V
IH
or V
IL
CE
≥
V
IH
, f = 0
V
DD
= Max.,
CE
≥
V
DD
– 0.2V,
V
IN
≥
V
DD
– 0.2V, or
V
IN
≤
0.2V, f = 0
Com.
Ind.
typ.
(2)
Com.
Ind.
Com.
Ind.
typ.
(2)
-8 ns
Min. Max.
—
—
—
—
—
—
—
—
100
110
75
15
20
1
1.5
0.05
-10 ns
Min. Max.
—
—
—
—
—
—
—
—
95
105
70
15
20
1
1.5
0.05
Unit
mA
I
SB
1
mA
I
SB
2
mA
Note:
1. At f = f
MAX
, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at V
DD
=3.3V, T
A
=25
o
C. Not 100% Tested.
CAPACITANCE
(1)
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Input/Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Max.
6
8
Unit
pF
pF
Note:
1. Tested initially and after any design or process changes that may affect these parameters.
4
Integrated Silicon Solution, Inc.
Rev. I
11/22/05
IS61LV6416
IS61LV6416L
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level
Output Load
Unit
0V to 3.0V
3 ns
1.5V
See Figures 1a and 1b
ISSI
®
1
2
3
319
Ω
3.3V
AC TEST LOADS
319
Ω
3.3V
4
5 pF
Including
jig and
scope
353
Ω
OUTPUT
30 pF
Including
jig and
scope
353
Ω
OUTPUT
5
6
7
Figure 1a.
Figure 1b.
READ CYCLE SWITCHING CHARACTERISTICS
(1)
(Over Operating Range)
Symbol
Parameter
Read Cycle Time
Address Access Time
Output Hold Time
CE
Access Time
OE
Access Time
OE
to High-Z Output
OE
to Low-Z Output
CE
to High-Z Output
CE
to Low-Z Output
LB, UB
Access Time
LB, UB
to High-Z Output
LB, UB
to Low-Z Output
-8 ns
Min. Max.
8
—
3
—
—
—
0
0
3
—
0
0
—
8
—
8
5
5
—
4
—
6
4
—
-10 ns
Min. Max.
10
—
3
—
—
—
0
0
3
—
0
0
—
10
—
10
5
5
—
5
—
6
5
—
-12 ns
Min. Max.
12
—
3
—
—
—
0
0
3
—
0
0
—
12
—
12
6
6
—
6
—
6
6
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
HZOE
(2)
t
LZOE
(2)
t
HZCE
(2
t
LZCE
(2)
t
BA
t
HZB
t
LZB
8
9
10
11
12
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.
Integrated Silicon Solution, Inc.
Rev. I
11/22/05
5
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