512 Kbit / 1Mbit / 4Mbit 3.0 Volt-only CMOS Flash Memory
FEATURES
•
Single Power Supply Operation
- Low voltage range: 2.70 V - 3.60 V
• Memory Organization
- IS39LV512: 64K x 8 (512 Kbit)
- IS39LV010: 128K x 8 (1 Mbit)
- IS39LV040: 512K x 8 (4 Mbit)
• High Performance Read
- 70 ns access time
• Cost Effective Sector/Block Architecture
- Uniform 4 Kbyte sectors
- Uniform 64 Kbyte blocks (sector group - except
IS39LV512)
• Data# Polling and Toggle Bit Features
• Hardware Data Protection
• Automatic Erase and Byte Program
- Build-in automatic program verification
-
Typical 16 µs/byte programming time
- Typical 55 ms sector/block/chip erase time
• Low Power Consumption
- Typical 4 mA active read current
- Typical 8 mA program/erase current
- Typical 0.1 µA CMOS standby current
• High Product Endurance
- Guarantee 100,000 program/erase cycles per
single sector (preliminary)
- Minimum 20 years data retention
• Industrial Standard Pin-out and Packaging
- 32-pin (8 mm x 14 mm) VSOP
- 32-pin PLCC
- Optional lead-free (Pb-free) package
• Operation temperature range
- IS39LV512/010
-40
o
C~+85
o
C
- IS39LV040
0
o
C~+85
o
C
IS39LV512 / IS39LV010 / IS39LV040
GENERAL DESCRIPTION
The IS39LV512/010/040 are 512 Kbit/1 Mbit/4 Mbit 3.0 Volt-only Flash Memories. These devices are designed
to use a single low voltage, range from 2.70 Volt to 3.60 Volt, power supply to perform read, erase and program
operations. The 12.0 Volt V
PP
power supply for program and erase operations are not required. The devices can
be programmed in standard EPROM programmers as well.
The memory array of IS39LV512 is divided into uniform 4 Kbyte sectors for data or code storage. The memory
arrays of IS39LV010/040 are divided into uniform 4 Kbyte sectors or uniform 64 Kbyte blocks (sector group -
consists of sixteen adjacent sectors). The sector or block erase feature allows users to flexibly erase a memory
area as small as 4 Kbyte or as large as 64 Kbyte by one single erase operation without affecting the data in
others. The chip erase feature allows the whole memory array to be erased in one single erase operation. The
devices can be programmed on a byte-by-byte basis after performing the erase operation.
The devices have a standard microprocessor interface as well as a JEDEC standard pin-out/command set. The
program operation is executed by issuing the program command code into command register. The internal control
logic automatically handles the programming voltage ramp-up and timing. The erase operation is executed by
issuing the chip erase, block, or sector erase command code into command register. The internal control logic
automatically handles the erase voltage ramp-up and timing. The preprogramming on the array which has not
been programmed is not required before an erase operation. The devices offer Data# Polling and Toggle Bit
functions, the progress or completion of program and erase operations can be detected by reading the Data#
Polling on I/O7 or the Toggle Bit on I/O6.
The IS39LV512/010/040 are manufactured on pFLASH™’s advanced nonvolatile CMOS technology. The devices
are offered in 32-pin VSOP and PLCC packages with 70 ns access time.
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
04/24/2013
1
IS39LV512 / IS39LV010 / IS39LV040
CONNECTION DIAGRAMS
I S 3 9 L V 5 12 I S 3 9 L V 0 10
I S 3 9 L V 0 4 0
WE#
WE#
WE#
A16
A12
A15
A18
A12
A15
A16
V
CC
A12
A15
NC
NC
V
CC
NC
NC
NC
A17
V
CC
I S 3 9 L V 0 4 0
I S 3 9 L V 0 10
I S 3 9 L V 5 12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
5
6
7
8
9
10
11
12
13
14
4
3
2
1
32
31
30
I S 3 9 L V 5 12 I S 3 9 L V 0 10
I S 3 9 L V 0 4 0
29
28
27
26
25
24
23
22
A14
A13
A8
A9
A11
OE#
A10
CE#
I/O7
A14
A13
A8
A9
A11
OE#
A10
CE#
I/O7
A14
A13
A8
A9
A11
OE#
A10
CE#
I/O7
15
16
17
18
19
20
21
I S 3 9 L V 5 12
I/O5
I/O5
I/O5
I/O1
I/O3
I S 3 9 L V 0 10
GND
I/O2
I/O4
I/O1
I/O3
IS39LV040
GND
I/O2
I/O4
I/O1
I/O3
32-Pin PLCC
IS39LV040 IS39LV010 IS39LV512
GND
I/O2
I/O4
I/O6
I/O6
I/O6
IS39LV512
IS39LV010
IS39LV040
A11
A9
A8
A13
A14
A17
WE#
V
CC
A18
A16
A15
A12
A7
A6
A5
A4
A11
A9
A8
A13
A14
NC
WE#
V
CC
NC
A16
A15
A12
A7
A6
A5
A4
A11
A9
A8
A13
A14
NC
WE#
V
CC
NC
NC
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE#
A10
CE#
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
OE#
A10
CE#
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
OE#
A10
CE#
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
32-Pin VSOP
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
04/24/2013
2
IS39LV512 / IS39LV010 / IS39LV040
PIN DESCRIPTIONS
SYMBOL
TYPE
DESCRIPTION
Address Inputs: For memory addresses input. Addresses are internally
latched on the falling edge of WE# during a write cycle.
Chip Enable: CE# goes low activates the device’s internal circuitries for
device operation. CE# goes high deselects the device and switches into
standby mode to reduce the power consumption.
Write Enable: Activate the device for write operation. WE# is active low.
Output Enable: Control the device’s output buffers during a read cycle.
OE# is active low.
Data Inputs/Outputs: Input command/data during a write cycle or output
data during a read cycle. The I/O pins float to tri-state when OE# are
disabled.
Device Power Supply
Ground
No Connection
A0 - A
MS(1)
INPUT
CE#
INPUT
WE#
INPUT
OE#
INPUT
I/O0 - I/O7
INPUT/
OUTPUT
VCC
GND
NC
Note:
1. A
MS
is the most significant address where A
MS
= A15 for IS39LV512, A16 for IS39LV010, and A18 for
IS39LV040.
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
04/24/2013
3
IS39LV512 / IS39LV010 / IS39LV040
BLOCK DIAGRAM
ERASE/PROGRAM
VOLTAGE
GENERATOR
HIGH V O L T A G E
SWITCH
I/O0-I/O7
I/ O BUF F ER S
WE#
CE#
OE#
COMMAND
REGISTER
C E, O E L O G I C
D AT A
LATCH
SENSE
AMP
ADDRESS
LATCH
Y-DECODER
X-DECODER
Y-GATING
MEMORY
ARRAY
A0 - A
M S
DEVICE OPERATION
READ OPERATION
The access of IS39LV512/010/040 are similar to
EPROM. To read data, three control functions must
be satisfied:
• CE# is the chip enable and should be pulled low ( V
IL
).
• OE# is the output enable and should be pulled low
( V
IL
).
• WE# is the write enable and should remains high (
V
IH
)
.
PRODUCT IDENTIFICATION
The product identification mode can be used to identify
the manufacturer and the device through hardware or
software read ID operation. See Table 1 for pFLASH™
Manufacturer ID and Device ID. The hardware ID mode
is activated by applying a 12.0 Volt on A9 pin, typically
used by an external programmer for selecting the right
programming algorithm for the devices. Refer to Table
2 for Bus Operation Modes. The software ID mode is
activated by a three-bus-cycle command. See Table 3
for Software Command Definition.
BYTE PROGRAMMING
The programming is a four-bus-cycle operation and
the data is programmed into the devices (to a logical
“0”) on a byte-by-byte basis. See Table 3 for Software
Command Definition. A program operation is activated
by writing the three-byte command sequence followed
by program address and one byte of program data
into the devices. The addresses are latched on the
falling edge of WE# or CE# whichever occurs later,
and the data are latched on the rising edge of WE# or
CE# whichever occurs first. The internal control logic
automatically handles the internal programming volt-
ages and timing.
A data “0” can not be programmed back to a “1”. Only
erase operation can convert the “0”s to “1”s. The Data#
Polling on I/O7 or Toggle Bit on I/O6 can be used to
detect the progress or completion of a program cycle.
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
04/24/2013
4
IS39LV512 / IS39LV010 / IS39LV040
DEVICE OPERATION (CONTINUED)
CHIP ERASE
The entire memory array can be erased through a chip
erase operation. Pre-programs the devices are not
required prior to a chip erase operation. Chip erase
starts immediately after a six-bus-cycle chip erase
command sequence. All commands will be ignored
once the chip erase operation has started. The devices
will return to standby mode after the completion of chip
erase.
SECTOR AND BLOCK ERASE
The memory array of IS39LV512/010/040 are organized
into uniform 4 Kbyte sectors. A sector erase operation
allows to erase any individual sector without affecting
the data in others. The memory array of IS39LV010/040,
excluding IS39LV512, are also organized into uniform
64 Kbyte blocks (sector group - consists of sixteen
adjacent sectors). A block erase operation allows to
erase any individual block. The sector or block erase
operation is similar to chip erase.
I/O7 DATA# POLLING
The IS39LV512/010/040 provide a Data# Polling fea-
ture to indicate the progress or completion of a program
and erase cycles. During a program cycle, an attempt
to read the devices will result in the complement of the
last loaded data on I/O7. Once the program operation
is completed, the true data of the last loaded data is
valid on all outputs. During a sector, block, or chip erase
cycle, an attempt to read the device will result a “0” on
I/O7. After the erase operation is completed, an attempt
to read the device will result a “1” on I/O7.
I/O6 TOGGLE BIT
The IS39LV512/010/040 also provide a Toggle Bit fea-
ture to detect the progress or completion of a program
and erase cycles. During a program or erase cycle, an
attempt to read data from the device will result a tog-
gling between “1” and “0” on I/O6. When the program
or erase operation is complete, I/O6 will stop toggling
and valid data will be read. Toggle bit may be accessed
at any time during a program or erase cycle.
HARDWARE DATA PROTECTION
Hardware data protection protects the devices from un-
intentional erase or program operation. It is performed
in the following ways: (a) V
CC
sense: if V
CC
is below 1.8
V (typical), the write operation is inhibited. (b) Write
inhibit: holding any of the signal OE# low, CE# high, or
WE# high inhibits a write cycle. (c) Noise filter: pulses
of less than 5 ns (typical) on the WE# or CE# input will
not initiate a write operation.
Table 1. Product Identification
Product Identification
Manufacturer ID
Device ID:
IS39LV512
IS39LV010
IS39LV040
1Bh
1Ch
3Eh
Data
9Dh
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
04/24/2013
5
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